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frequency spectrum of clk jitter in pnoise simulation

scc28

Hi, I have a question about jitter simulation in cadence pnoise. This is concerning a driven circuit, not an autonomous circuit like an oscillator. When I plot Jee of a clock generated by a few inverters and an ideal driven source after completing both PSS and Pnoise, I seem to be able to plot the phase noise frequency spectrum beyond fs. Also, I can integrate beyond fs/2 to find rms jitter. I don't understand why this is allowed or what the result really means since phase noise should only be valid from 0 to fs/2. I did prove that the spectrum looks the same around 0, fs, 2fs, 3fs....(I kept quite a few sidebands) However, what is the engine underneath pnoise jitter jee? Why is it plotting beyond fs/2? Thanks.

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