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interleaving buses

AlbertoGS

Hello,

I would like to interleave several buses.


Take the buses

A<0:1>, B<0:1>


I would like to have the output:

A<0>,B<0>,A<1>,B<1>


The buses I intend to interleave are much bigger so the explicit notation is not feasible


I had a look at the Schematic Editor User Guide but I don't seem to find how to do it. Is there anyway to do this without resoting to use a verilogA module?

Many thanks

  • Andrew Beckett

    You don't need to use VerilogA (I'm not sure how that would help anyway), but there's a previous thread on this topic where I referenced an enhancement request for a similar idea, plus showed some SKILL how to build the expression for you (you'd have to adapt it to suit your needs).

    Regards,

    Andrew

  • AlbertoGS

    Hi Andrew,

    Thanks for your help. I was planning using a verilogA module with a for loop that uses the loop index (genvar) as argument of a case statement (loop index modulo of the number of buses to interleave) in which the concurrent assignments are done.

    I ll have a look at your SKILL code, although explicitly writing 512*16 wire names seems not ideal

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