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Post layout simulation error in 45nm technology

akchetana

Hello everyone,
I want to perform the post-layout simulation for 6T SRAM cell in Cadence for 45nm technology. However, I am trying  with a simple inverter first. Both the DRC and LVS are cleared. Now when I try to do post-layout it shows me an error while adding the RCX file. However, the simulation succeeded for 180nm technology for the same circuit. Maybe this is because the RCX file is not attached or not found for 45nm technology. Can anyone tell me the way to attach these files?

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