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transient simulation convergence cadence : fully differential sample and hold

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Hi all

I am trying to simulate a fully differential sample and hold using ideal verilog A model, although the switches are using mosfets.

Attached is the input.scs file and the error messages.

Also , i would like to know , what are the guidelines to be followed to avoid these issues. I face issues on convergence every now and then ,but find it difficult to pinpoint the exact location of the problem

Also, here is the screenshot of the circuit i am trying to simulate.

Thanks

cadence_error_input.zip

  • Andrew Beckett

    First of all, remove the minstep and maxstep parameters from your transient analysis (especially the minstep). Other than that it's hard to debug without access to the full data (models and your Verilog-A model for the amplifier, which is probably the most likely cause of the convergence failures, from a wild guess).

    You can run spectre with a command line switch, +diagnose, which will output more information. You are just about running a recent enough version of spectre to be able to use this (although it would be better to use something newer for better diagnostics).

    Other than that, I would suggest contacting customer support so we can take a look at this with all the data provided (we should be able to obtain the model files from the foundry that way).

    Regards,

    Andrew.

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