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Verilog IN error

magarwal

I am importing a synthesized verilog file using the CIW menu File -> Import -> Verilog. The import fails, and the verilogIn.log file displays the following 2 lines only:

ERROR (VERILOGIN-540): visadev load failed

INFO (VERILOGIN-206): End of Logfile

Any thoughts? 

  • Andrew Beckett

    This looks like this support solution. From that, I suspect you have mixed versions of tools in your UNIX $PATH - some where you've including the "tools/inca/bin" path from some stream in your path.

    You didn't mention any tool versions used.

    Can you just post what "echo $PATH" shows? Please provide it exactly, as-is - so I can check if anything looks suspicious.

    Regards,

    Andrew.

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