Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 16093
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Verilog IN error

magarwal

I am importing a synthesized verilog file using the CIW menu File -> Import -> Verilog. The import fails, and the verilogIn.log file displays the following 2 lines only:

ERROR (VERILOGIN-540): visadev load failed

INFO (VERILOGIN-206): End of Logfile

Any thoughts? 

  • Andrew Beckett

    This looks like this support solution. From that, I suspect you have mixed versions of tools in your UNIX $PATH - some where you've including the "tools/inca/bin" path from some stream in your path.

    You didn't mention any tool versions used.

    Can you just post what "echo $PATH" shows? Please provide it exactly, as-is - so I can check if anything looks suspicious.

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.