Post-layout simulation with Parasitic R

Hi,

I have a weird problem when I do post-layout simulation. In my circuit I have a lot of stuff including a bunch of switches connected to a resistor ladder. These switches are connected to reference voltages. I use PVS to do QRC.

My circuit breaks when I extract parasitic resistance. I noticed it is only because of those reference voltages connected to the switches and the resistor ladder. I included the reference voltages as power nets in QRC setup (I think I am not supposed to do that) and the post layout simulation worked perfectly, and I think it is because all nets recognized as power nets will not have parasitic elements.

In order to debug, I did the followings:

1) Simulation: The length of the reference wire is 1mm with the width of 4um, so I calculated the resistance and added the value to the schematic and run a transient  simulation. But the circuit worked fine even with the modeled parasitic resistance.

2) Post-layout simulation: I wanted to see the voltage drop on that 1mm wire right before being fed to a switch. So I cut that wire right before the switch and added two pins and connected them on the top level (Shown in the attached figure). Now that 1mm wire is connected to the switch on the top level with an ideal wire (basically the length of the wire is decreased from 1 mm to ~0.998 mm). Again I did the post layout simulation and the circuit worked fine! (The reference voltage parasitic R was extracted too). I have no idea why when I added two pins and connected the wires on the top level I got a different result. 

I appreciate if anyone can help me figure out what the problem is!