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  3. netlist generation with SystemVerilog netlister plugin

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netlist generation with SystemVerilog netlister plugin

jach78
jach78 over 8 years ago

Hi All,

I don't know how to force the netlister to not use positional convention when instantiating modules. I would like the netlister to use the explicit mapping of the signals:

example

I would like to have:

cellname inst_name(.sig1(net1),.sig2(net2)); 

and not


cellname inst_name(net1,net2);

I have tried the "Netlist Explicitly" option. I tried the "Generate Pin Mapping" option. But nothing happens.

Thanks in advance,

Jack.

 

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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    Jack,

    I suggest you contact customer support. Netlist Explicitly should do this - but maybe there is some complexity in your data which is causing this to not work - so we'd need to see it. Or you may be clobbering the setting in the .simrc file, say.

    Regards,

    Andrew.

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  • jach78
    jach78 over 8 years ago

    Hi Andrew,

    I was not able to locate my .simrc file. I thought it was automatically managed by the netlister user interface configuration. Am I wrong?

    What do you mean for "clobbering"?

    Best regards,

    Jack.

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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    Hi Jack,

    The netlister UI creates a file called "si.env" in the run directory with the netlister settings, but if these have been overridden in a .simrc (which could exist in various places - working dir, home dir, <ICinstDir>/tools/dfII/local - and potentially others if CSF has been enabled for .simrc - try typing "cdswhich -all .simrc" and "cdswhich -lookupconfig .simrc") - that's what I meant by "clobbering'.

    That's why I suggested going to customer support - that way we can have a far more interactive discussion to look at your setup and specific situation to understand why it isn't working.

    Regards,

    Andrew.

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