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Node name used in .measure statement

roopakvasa

HI,

Consider the following meas statement.

.meas tran c2c_read_to_write_blrst_min min v(SEGARRAYX2.SEG0.BANK_MAX.HBANK.LBL.LBLX4_0.\xxl_blx4\/xblx10\/xp5\/mp0.g ) from=cycle1_start to=cycle1_end

.meas tran c2c_read_to_write_blrst_min min v(SEGARRAYX2.SEG0.BANK_MAX.HBANK.LBL.LBLX4_0.\BLRST ) from=cycle1_start to=cycle1_end

Now both the above statements specify the same node. 

By my knowledge the first one considers the parasitic upto the gate of the device. So thats the advantage over the 2nd statement. But the disadvantage is that 1st meas statement can not be used on pre layout netlist.

So is there any where we can write meas statements which work on postlayout as well as pre layout ?

Something like : SEGARRAYX2.SEG0.BANK_MAX.HBANK.LBL.LBLX4_0.\n_blrst_xxl_blx4\/xblx10\/xp5\/mp0.g

 

Thanks.

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  • Andrew Beckett

    Assuming you're talking about spectre (you didn't say - in fact very few details about the nature of the extraction, the simulator used, and so on), then I think the answer is no.

    In ADE there's the ability to use "out of context probing" to probe near the transistor in the schematic and it will translate to the extracted node, but even then the node names are different for pre-and post layout. I don't know what extraction tool you're using (not that I think it makes much difference).

    Fundamentally the problem is that the simulator doesn't know the relationship between the pre and post layout netlists.

    One other possibility (and I'm a little loathed to suggest this) is to use DSPF and then DSPF stitching of the DSPF onto the pre-layout netlist. However, even then, the problem is that the node name pre-layout will be common for the entire net and so it won't know which part of the net you really want post-layout (plus DSPF stitching is always a little challenging to be accurate and complete, in any tool).

    Regards,

    Andrew.

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  • Andrew Beckett

    Assuming you're talking about spectre (you didn't say - in fact very few details about the nature of the extraction, the simulator used, and so on), then I think the answer is no.

    In ADE there's the ability to use "out of context probing" to probe near the transistor in the schematic and it will translate to the extracted node, but even then the node names are different for pre-and post layout. I don't know what extraction tool you're using (not that I think it makes much difference).

    Fundamentally the problem is that the simulator doesn't know the relationship between the pre and post layout netlists.

    One other possibility (and I'm a little loathed to suggest this) is to use DSPF and then DSPF stitching of the DSPF onto the pre-layout netlist. However, even then, the problem is that the node name pre-layout will be common for the entire net and so it won't know which part of the net you really want post-layout (plus DSPF stitching is always a little challenging to be accurate and complete, in any tool).

    Regards,

    Andrew.

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