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Node name used in .measure statement

roopakvasa

HI,

Consider the following meas statement.

.meas tran c2c_read_to_write_blrst_min min v(SEGARRAYX2.SEG0.BANK_MAX.HBANK.LBL.LBLX4_0.\xxl_blx4\/xblx10\/xp5\/mp0.g ) from=cycle1_start to=cycle1_end

.meas tran c2c_read_to_write_blrst_min min v(SEGARRAYX2.SEG0.BANK_MAX.HBANK.LBL.LBLX4_0.\BLRST ) from=cycle1_start to=cycle1_end

Now both the above statements specify the same node. 

By my knowledge the first one considers the parasitic upto the gate of the device. So thats the advantage over the 2nd statement. But the disadvantage is that 1st meas statement can not be used on pre layout netlist.

So is there any where we can write meas statements which work on postlayout as well as pre layout ?

Something like : SEGARRAYX2.SEG0.BANK_MAX.HBANK.LBL.LBLX4_0.\n_blrst_xxl_blx4\/xblx10\/xp5\/mp0.g

 

Thanks.

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  • Andrew Beckett

    If it's C-only, then I don't see why there would be any difference. However, in that case, I can't see why you would have two different node names in the same extracted subckt; if they were at different levels of hierarchy (which they're not, from what you've written) then it would be possible to access the same node two different ways, but if they're in the same subckt, there must be something between them in order to distinguish them.

    Without knowing what the data from the Synopsys extraction tool looks like, I can't explain why both nodes would even exist in the netlist. If it's c-only though, I can't see why there would be any benefit probing one place over the other, because all capacitors would be hanging off the same node. Perhaps you should ask Synopsys, since this would be a function of their extractor rather than the behaviour of the Cadence Spectre simulator?

    Regards,

    Andrew.

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  • Andrew Beckett

    If it's C-only, then I don't see why there would be any difference. However, in that case, I can't see why you would have two different node names in the same extracted subckt; if they were at different levels of hierarchy (which they're not, from what you've written) then it would be possible to access the same node two different ways, but if they're in the same subckt, there must be something between them in order to distinguish them.

    Without knowing what the data from the Synopsys extraction tool looks like, I can't explain why both nodes would even exist in the netlist. If it's c-only though, I can't see why there would be any benefit probing one place over the other, because all capacitors would be hanging off the same node. Perhaps you should ask Synopsys, since this would be a function of their extractor rather than the behaviour of the Cadence Spectre simulator?

    Regards,

    Andrew.

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