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Assura Omits Cell Pins During Schematic Netlisting

jschmitz

I am running Assura LVS on a DFII top-level schematic, containing a digital instance from Encounter that uses a verilog netlist instead of a DFII schematic.  After seeing odd mismatches, I used vldbToVnl to convert the LVS *.snn schematic netlist to an ASCII *.vnl netlist.  There is an issue in the cell interface definition for the verilog block.  It has dozens of pins that are correct, but is missing a few I/O pins.  Of note, the missing pins were added to the cell after the initial import to Virtuoso/OA.  When I added these pins, I streamed in the new layout and abstract views, and modified the symbol view by hand to reflect the new pins.

Any idea why Assura's schematic netlister would not see the new pins?

View List: "auLvs cmos_sch schematic symbol"
Stop List: "auLvs cmos_sch symbol"
Views in my digital cell: "abstract layout symbol" and the verilog netlist is added to the LVS run via avReadVerilog()

Tool Versions:
IC 6.1.6-64b.500.14
Assura 4.1_USR4
QRC 12.1.1-s695
Encounter 13.17-s018_1

Parents
  • jschmitz

    I discovered that the underlying problem was a naming conflict between my own library and the standard cell library provided by the foundry.  Since the verilog netlist specified only a cell name and not the library, it caused the cells found in multiple libraries to be unbound during netlisting.  Any pins that connected solely to those cells were also removed.  While I imagine it is possible to bind the verilog to a specific library, I chose to rename the conflicting cells, and LVS now works properly.

Reply
  • jschmitz

    I discovered that the underlying problem was a naming conflict between my own library and the standard cell library provided by the foundry.  Since the verilog netlist specified only a cell name and not the library, it caused the cells found in multiple libraries to be unbound during netlisting.  Any pins that connected solely to those cells were also removed.  While I imagine it is possible to bind the verilog to a specific library, I chose to rename the conflicting cells, and LVS now works properly.

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