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howto disable port-order check for vmsUpdateCellViews ?

Emulator

Hello,

I try to apply SV netlister, so I need to run the vmsUpdateCellViews for systemverilog models (stored on an external repository) before.

As I have to enable the cross-check wrt to symbol and module port consistency (port number and port names), I would like to disable the portOrder check during vmsUpdateCellViews.

Setting following variables didn't help out in IC 6.1.6:

disablePortOrderPopup=nil

vicCheckPinOrder=nil.

As the connections are explicit, the portOrder may be ignored for symbol and systemverilog module.

Do you have any further hints on disabling it ?

Thanks in advance,

Gregor 

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