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determine the simulation time of compact model in verilog-A

samer1

I developed a compact model for a memristor and comparing it to other models in terms of convergence time. I have three models: exponential, linear and polynomial. I expect to see difference in convergence time. Yet, CPU transient time is always the same for different circuit. I tried different circuits and different transient analysis time yet they are all still the same. The models are all impelemented in verilog A. 

Any advice what I can do?

First, How do I measure the simulation time? is it the transient CPU time?

If it is the transient CPU time, any ideas why they are all converging with same simulation time. I mean, they are different functions with different complexities? How could they all have the same convergence time?

Thanks in advance

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  • chanakaya
    Hi Serif,

    This is not the correct forum for this question. You question is on simulation and modeling and this particular forum is focused on SKILL.

    On your question, I am not clear on what you mean by convergence time. Spectre reports the runtime for transient analysis (both CPU and wall time). You can use wall time as an indication provided that you are running all sims on the same machine and there is no other jobs loading the machine. Otherwise, use CPU time to get an idea.

    In addition, it might be good to run spectre with +diagnose, +ahdllint to get more useful information in the log file on you VerilogA model.

    --at
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  • chanakaya
    Hi Serif,

    This is not the correct forum for this question. You question is on simulation and modeling and this particular forum is focused on SKILL.

    On your question, I am not clear on what you mean by convergence time. Spectre reports the runtime for transient analysis (both CPU and wall time). You can use wall time as an indication provided that you are running all sims on the same machine and there is no other jobs loading the machine. Otherwise, use CPU time to get an idea.

    In addition, it might be good to run spectre with +diagnose, +ahdllint to get more useful information in the log file on you VerilogA model.

    --at
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