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  3. determine the simulation time of compact model in verilog...

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determine the simulation time of compact model in verilog-A

samer1
samer1 over 8 years ago

I developed a compact model for a memristor and comparing it to other models in terms of convergence time. I have three models: exponential, linear and polynomial. I expect to see difference in convergence time. Yet, CPU transient time is always the same for different circuit. I tried different circuits and different transient analysis time yet they are all still the same. The models are all impelemented in verilog A. 

Any advice what I can do?

First, How do I measure the simulation time? is it the transient CPU time?

If it is the transient CPU time, any ideas why they are all converging with same simulation time. I mean, they are different functions with different complexities? How could they all have the same convergence time?

Thanks in advance

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  • samer1
    samer1 over 8 years ago
    Thanks chanakaya and Andrew for your help. Sorry for putting this in the wrong place. This is my first time to participate in Cadence forums.

    best,
    Sherif
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  • samer1
    samer1 over 8 years ago
    Thanks chanakaya and Andrew for your help. Sorry for putting this in the wrong place. This is my first time to participate in Cadence forums.

    best,
    Sherif
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