Stats

  • Locked Locked
  • Replies 1
  • Subscribers 126
  • Views 1623
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Assura DRC/LVS error

Alpacca

Hello there,

I'm making an OTA layout in cmhv7sf technology. When I run DRC I get errors that 8 transistors have no body contact, while there are substrate and n-well contacts. Because of thsee errors LVS is failing due to those 8 unmatched transistors.

Thanks in advance for your help!

Here is DRC result:

Here is layout:

  • Quek

    Hi Lidia

    You might want to check the following:

    a. Does the PDK user guide say that you need to manually draw some extra layers to create substrate/well contacts?

    b. Are there any switches in DRC/LVS decks that need to be enabled so that the contacts can be extracted?

    c. Instead of manually adding those contacts, how about enabling the "body tie" option on the mos pcell? If this resolves the problem, check the layers in the automatically created body tie and compare it against your current contacts.


    Best regards
    Quek

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.