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layout xl automatic routing of the gate

nicola91it

Hi to everyone.

I am working at the layout of a cellview and I am using DFM rules. If I edit the properties of transistors I can select to automatically place the contacts on the poly for the gate: however, this determines only one contact and the DFM doesn't allow only one contact for M1_PO, in order to avoid high Rc. So. it seems that in my case I have to route all the gates manually. Is there any option to avoid all this effort? Thanks and regards.

Nicola

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  • Andrew Beckett

    This is going to be a function of how the "DFM" option has been implemented in the PCell for the device for the specific PDK you're using; it's not a Cadence-supplied setting, but a customisation from the foundry. So you need to contact the foundry to understand what the options are.

    You could potentially use the wire editor (or router) in VLS XL to do this, telling it you want a minimum number of cuts as 2 in the wire assistant, but I'm not sure that's what you're asking here - this would then be a semi-automatic option. If you want it done by the device itself, you'll need to contact the foundry as it's their PDK that is behaving this way.

    Regards,

    Andrew.

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  • Andrew Beckett

    This is going to be a function of how the "DFM" option has been implemented in the PCell for the device for the specific PDK you're using; it's not a Cadence-supplied setting, but a customisation from the foundry. So you need to contact the foundry to understand what the options are.

    You could potentially use the wire editor (or router) in VLS XL to do this, telling it you want a minimum number of cuts as 2 in the wire assistant, but I'm not sure that's what you're asking here - this would then be a semi-automatic option. If you want it done by the device itself, you'll need to contact the foundry as it's their PDK that is behaving this way.

    Regards,

    Andrew.

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