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Create an additional layer for layout

samer1

I want to create and additional layer for layout and define its design rules for a specific process technology that I will be working with. 

For example, I want to create a layer between M1 and M2.

Can someone direct me to what I should do?

Sherif

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  • samer1
    Hi Quek

    Thanks for you help. Your method worked perfectly with me. I am now working on LVS rulefile and i am facing an issue with the layout extraction . Unfortunately, I am using Calibre so I do not know if you are familiar with it or not. But may be as I explain the problem, you might be able to give me some insight to what the problem might be.

    My stack is M1>VRB>RR>VRT>M2

    where RR is the device defined as metal in the techfile, VRB and VRT are two layers that I defined as vias (cut).

    My test circuit is:

    MUX1>RR>MUX2, where the output of each mux connects to one terminal of my two terminal device represented by RR.

    The LVS extracts MUX1, MUX2 and RR all seperately. they do not connect?
    Do you have any ideas what the problem might be?

    Thanks in advance
Reply
  • samer1
    Hi Quek

    Thanks for you help. Your method worked perfectly with me. I am now working on LVS rulefile and i am facing an issue with the layout extraction . Unfortunately, I am using Calibre so I do not know if you are familiar with it or not. But may be as I explain the problem, you might be able to give me some insight to what the problem might be.

    My stack is M1>VRB>RR>VRT>M2

    where RR is the device defined as metal in the techfile, VRB and VRT are two layers that I defined as vias (cut).

    My test circuit is:

    MUX1>RR>MUX2, where the output of each mux connects to one terminal of my two terminal device represented by RR.

    The LVS extracts MUX1, MUX2 and RR all seperately. they do not connect?
    Do you have any ideas what the problem might be?

    Thanks in advance
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