Regarding verilogA model of a discrete time delay free integrator

Hi,

I am trying to implement a delay free integrator with transfer function = 1/(1-Z^-1) using the model writer of the cadence virtuoso  the corresponding generated code is mentioned below.

Problem: When an input sampled signal of 1kHz and 900 microV ( = V_peak) is applied the output of the integrator is cosine but with output magnitude from 0 to 73 mV.  Is there any problem with code or is there any special setting is required. If the input is 100 mV (= V_peak) then output of the integrator is in kVs.

Please help.

I am attaching screenshots of the schematic and transient response of the integrator (bottom is integrator output while top one is sample and hold output)

//     FUNCTION: Z-domain Filter
//      VERSION: $Revision: 2.8 $
//       AUTHOR: Cadence Design Systems, Inc.
//
// GENERATED BY: Cadence Modelwriter 2.31
//           ON: Thu Feb 02 08:59:10 IST 2017
//
// Description:  N degree Transfer functions of  H(z)
//    May be specified as a Polynomial or as Poles and Zeros.
//
//    Complex Poles and Zeros must have conjugates.
//
//
//    This model is an example, provided "as is" without express or
//    implied warranty and with no claim as to its suitability for
//    any purpose.
//
// PARAMETERS:
//   first = Delay before taking first sample [S]
//    samp = Sampling period [S]
//   trans = Transtion time [S]
//

`include "discipline.h"
`include "constants.h"

//  model ztrans



//   Z-domain in Numerator-Denominator form
//   Filter order is:  1 / 2
 
module ztrans (vin, vout);
  input vin;
  output vout;
  electrical vin, vout;
  parameter real samp = 3.90u from (0:inf);      



//               nxN  is  numerator of degree N.
//               dxN  is  denominator of degree N.
  parameter real nx0 = 1.0;
  parameter real dx0 = 1.0;
  parameter real dx1 = -1;

    analog begin
        V(vout) <+  zi_nd( V(vin), { nx0 },
                 { dx0, dx1 }, samp);
    end

endmodule