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Assura problems with feedthrough caps

ManuelSuarez

Hi everybaby,

I am getting extrange behabiour in assura. I have 2 digital blocks A and B sintetized independently and  we have added prefixes A_... B_... to the corresponding subcircuits in to avoid problems when put together.

When placed together, they have independent power rails.

The LVS are clean if run independently but when they are put together i get a lot of parameter mismatch in cells made up by feedthrough cells from the std. library of the technology.

Suppose i have the cells feed1, feed2...feedn from the standard lib. When I open the LVS Debug Env.  and i open the mismatches it shows that what is in the schematic feed2 is in the layout feed7 (for example). Like this many other similar.

I found out the ambiguities message during the LVS run as weel.

For me looks like assura is mixing the feedthrough cells. Since  the feed cells in a block are all connected to the same VDD and GND the circuits match (instances, nets...) but the parameters not.

The autoswappin option is "off".

I hope somebody can elucidate some solution the problem or hint.

Best regards,

Manuel

  • Manuel,

    Debugging this in a forum without being able to see the data would be very hard. Please can you contact customer support for this.

    Regards,

    Andrew.

  • Hi Andrew,
    Yes, i guess it would be difficult but thanks anyway.
    I progress a little bit. Just in case it can be useful to somebody: I am having around 10000 ambiguities but if I increase the threshold to 20000 assura provides a clean LVS.
    The clean LVS does not satisfy me completely and I am try to understand the nature of these ambiguities to avoid them when possible and understand why assura expands the feedthrough cells (they are MOS caps with D and S shorted to the same potential).
    Somebody can tell me when or in which conditions assura expands a cell? in my case schematic hierarchy and layout hierarchy are equal.

    Regards,

    Manuel

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