Stats

  • Locked Locked
  • Replies 3
  • Subscribers 125
  • Views 17778
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cadence Virtuoso: Import a large verilog netlist to cadence schematic

oAwad

Hello all,

I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors:

Error: Net "v_CALCULATION_CNTR<7:0>" shorted to net "N5512,N5511,N5510,N5509,N5508,N5507,N5506,SYNOPSY S_UNCONNECTED__0".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5507>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5512>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5509>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5508>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5511>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5510>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5506>" from net "v_CALCULATION_CNTR<7:0>".
INFO (SCH-1172): There were 8 errors and 0 warnings found in "NangateOpenCellLibrary key_expansion_KEY_SIZE0 schematic".

Moreover, I can see lots of unconnected wires like the attached picture

cadence.png

This verilog netlist was exported from SoC Encounter from a layout with no geometry or connectivity violations. 

Any suggestions ?

EDIT: the unconnected wires are probably due to some floating output pins of std cells that are not used in the design and I don't see errors complaining about them.

  • Andrew Beckett

    Not without seeing the netlist (I can't see the picture - it is very small) and also I'd suggest you try something rather less ancient than the IC version you're trying.

    Andrew.

  • oAwad
    Thanks Andrew for your reply. I'll try a more recent IC version, but one more simple question.. in the design verilog netlist every std cell has "VDD"&"VSS" as power ports, while in the std cell Library, the std cells schematics has "VDD!"&"VSS!" as their ports (I understand what you told me before, but can this be a mismatch ?).
    If it will not result in mismatch, then I should specify "VDD"&"VSS" as global power nets in Verilog In window, correct ?

    Thank you!
  • Andrew Beckett

    As I've said before, having power nets in the verilog won't help you since the symbols don't have power and ground nets. Similarly the verilog descriptions of the standard cells don't have power and ground nets. It's irrelevant what you specify as the global nets in the Verilog In form because those nets wouldn't be in the Verilog netlist (unless you've used the inherited connections trick I mentioned before, or you've got explicit pins everywhere, which probably doesn't make sense as part of a flow).

    I suspect all you need to do is ensure that the top level pins (on your P&R block) are called VDD! and VSS! or you have made those equivalent to VDD and VSS respectively (I expect Calibre LVS allows you to do this).

    I doubt it's essential for the pins to match on the netlist and layout at each and every level of hierarchy, or there's probably a way  of mapping them somehow in Calibre. However, not a tool I have really used (as I work for Cadence not Mentor).

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.