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Oversampling clock and data recovery for SerDes communication

bitan1990

Dear Friends, I am newbie to hardware design. I have a task to design a burst mode CDR. Typically it should have very fast frequency acquisition time.
In my system, I have a 8 phase clock input. I am sampling my data with this clock. Now I am searching for an algorithm to detect the phase at the mid point of the data (thereby locks in no time). I think I should need a phase selector which is driven by this algorithm.
There are papers in the web related to the topic. But being new to this field some tips and examples would be very helpful.

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