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VHDL-AMS library issue?

srana01
I'm trying to simulate a simple resistor implementation using VHDL-AMS in cadence. The VHDL-AMS code is as follows:

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;
use ieee.mechanical_systems.all;
use std.textio.all;
use ieee.math_real.all;

entity resistor is
port (terminal p1, p2: electrical);
end entity resistor;

architecture ideal of resistor is
constant R : real := 10.0e3;
quantity v across i through p1 to p2;

begin
i == v/R;
end architecture ideal;


The extraction step was initially not working (problems with finding libraries). After I added the following path to the cds.lib file the extraction started working without any errors and warnings.

INCLUDE /usr/local/cadence/2014-15/INCISIV141/tools.lnx86/inca/files/IEEE_vhdlams/cds.lib.

However, when I create a simple testbench and try to simulate the resistor, I get the following error:

Fatal error found by spectre in `testSim__TB_res__schematic__0x10000001',
        during circuit read-in.
    FATAL (SFE-82):
        "/home/eexsr/linux/testCadence/Sim/TB_res/ams/config/netlist/ihnl/testSim/TB_res/schematic/verilog.vams"
        16: `I0': An instance of `resistor', port name `p1' not found.
    FATAL (SFE-82):
        "/home/eexsr/linux/testCadence/Sim/TB_res/ams/config/netlist/ihnl/testSim/TB_res/schematic/verilog.vams"
        16: `I0': An instance of `resistor', port name `p2' not found.

I feel the problem is still with finding the libraries as the nature of the ports is electrical, which should be defined in the IEEE library.

Could you please point me in the right direction?

Many thanks!
Parents

  • The problem is that your entity is called resistor which is a built-in primitive in the analog solver, and because of that the terminal names don't match. 

    I believe you're using the older "Cell-Based Netlisting" flow (I get the same errors if you use CBN). The newer "AMS Unified netlister with irun" flow diagnoses this a bit more clearly:

    ncelab: *F,OSSPBT: 'testres.I0' of cell 'resistor' is a SPICE built-in primitive. It cannot be configured to another view like 'External HDL' via Cadence Hierarchy Editor.

    If you change the entity name to something else (e.g resideal or myres), it works fine, even with Cell-Based Netlisting.

    Regards,

    Andrew.

Reply

  • The problem is that your entity is called resistor which is a built-in primitive in the analog solver, and because of that the terminal names don't match. 

    I believe you're using the older "Cell-Based Netlisting" flow (I get the same errors if you use CBN). The newer "AMS Unified netlister with irun" flow diagnoses this a bit more clearly:

    ncelab: *F,OSSPBT: 'testres.I0' of cell 'resistor' is a SPICE built-in primitive. It cannot be configured to another view like 'External HDL' via Cadence Hierarchy Editor.

    If you change the entity name to something else (e.g resideal or myres), it works fine, even with Cell-Based Netlisting.

    Regards,

    Andrew.

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