• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Error while simulating verilog-A block

Stats

  • Locked Locked
  • Replies 6
  • Subscribers 125
  • Views 16723
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Error while simulating verilog-A block

tangudubharat
tangudubharat over 8 years ago

Hai,


I am trying to simulate one schematic which includes the variable capacitor (designed using Verilog-A).  While simulation, I am getting some errors which I could not figure out.

Can someone help me?  I am pasting the log file


Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 15.1.0.385.isr3 32bit -- 22 Feb 2016
Copyright (C) 1989-2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: Newton   Host: Newton.vlsi   HostID: 10AC3F0A   PID: 76922
Memory  available: 674.8651 MB  physical: 3.9027 GB
Linux   : Red Hat Enterprise Linux Client release 6.9 (Santiago)
CPU Type: Intel(R) Xeon(R) CPU E5-1607 v3 @ 3.10GHz
All processors running at 1200.0 MHz
        Socket: Processors
        0:       0,  1,  2,  3
        
System load averages (1min, 5min, 15min) : 19.0 %, 18.0 %, 9.5 %


Simulating `input.scs' on Newton.vlsi at 12:30:29 AM, Sun Apr 9, 2017 (process id: 76922).
Current working directory: /home/Newton/simulation/varcap_test/spectre/schematic/netlist
Command line:
    /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/bin/spectre  \
        input.scs +escchars +log ../psf/spectre.out +inter=mpsc  \
        +mpssession=spectre0_60350_2 -format psfxl -raw ../psf  \
        +lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 76922

Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libphilips_o_sh.so ...
Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Reading file:  /home/Newton/simulation/varcap_test/spectre/schematic/netlist/input.scs
Reading file:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_bjt_v121.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_bjt_v121.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_mimcap_v101.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_mimcap_v101.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg18bpw_v123.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg18bpw_v123.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg33bpw_v123.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg33bpw_v123.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_res_v141.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_res_v141.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_res_v141.va
Reading link:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading link:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_lvt18_v113.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_lvt33_v113.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg18_v124.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg18_v124.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg33_v114.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg33_v114.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_zvt18_v121.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_zvt18_v121.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_zvt33_v113.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/core_rf_v2d4.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/core_rf_v2d4.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/io_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/io_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/l_slcr20k_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/l_slcr20k_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mimcapm_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mimcapm_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mim.va
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/pad_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/pad_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnhr_rf_v2d4.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnhr_rf_v2d4.mdl.scs

Warning from spectre in `rnhr_rf', during circuit read-in.
    WARNING (SFE-2296): "/home/Newton/Documents/UMC180/UMC_18_CMOS/../Models/Spectre/./rnhr_rf_v2d4.mdl.scs" 8: The inline subckt definition `rnhr_rf' does not contain any inline components. The `inline' qualifier will therefore be ignored.

Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnnpo_rf_v2d4.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnnpo_rf_v2d4.mdl.scs

Warning from spectre in `rnnpo_rf', during circuit read-in.
    WARNING (SFE-2296): "/home/Newton/Documents/UMC180/UMC_18_CMOS/../Models/Spectre/./rnnpo_rf_v2d4.mdl.scs" 8: The inline subckt definition `rnnpo_rf' does not contain any inline components. The `inline' qualifier will therefore be ignored.

Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnppo_rf_v2d4.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnppo_rf_v2d4.mdl.scs

Warning from spectre in `rnppo_rf', during circuit read-in.
    WARNING (SFE-2296): "/home/Newton/Documents/UMC180/UMC_18_CMOS/../Models/Spectre/./rnppo_rf_v2d4.mdl.scs" 8: The inline subckt definition `rnppo_rf' does not contain any inline components. The `inline' qualifier will therefore be ignored.

Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/vardiop_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/vardiop_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/varmis_18_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/varmis_18_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_diode_v113.mdl.scs
Reading file:  /home/Newton/Desktop/work/PhD_work/varcap/veriloga/veriloga.va
Time for NDB Parsing: CPU = 91.986 ms, elapsed = 170.808 ms.
Time accumulated: CPU = 104.983 ms, elapsed = 170.812 ms.
Peak resident memory used = 31.9 Mbytes.


The CPU load for active processors is :
        Spectre  0 (62.5 %)      1 (43.8 %)      2 (43.8 %)      3 (29.4 %)
        Other   
Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB//cbca1efacc0b5f822e93584eeafed5ab.varcap.ahdlcmi/ (775)
Opening directory input.ahdlSimDB//cbca1efacc0b5f822e93584eeafed5ab.varcap.ahdlcmi/Linux/ (775)
Compiling ahdlcmi module library.

Warning from spectre during AHDL read-in.
    WARNING (VACOMP-2397): Compilation failed when using pipe build. Bytecode flow will be used for encrypted VerilogA, and normal file compilation will be used for unencrypted VerilogA.

Compiling ahdlcmi module library.

Error found by spectre during AHDL read-in.
    ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//cbca1efacc0b5f822e93584eeafed5ab.varcap.ahdlcmi/Linux//..//ahdlcmi.out for details. Contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
    ERROR (SFE-91): Error when elaborating the instance varcap. Simulation should be terminated.

Time for Elaboration: CPU = 37.994 ms, elapsed = 1.04592 s.
Time accumulated: CPU = 142.977 ms, elapsed = 1.21686 s.
Peak resident memory used = 38.1 Mbytes.


Aggregate audit (12:30:30 AM, Sun Apr 9, 2017):
Time used: CPU = 144 ms, elapsed = 1.22 s, util. = 11.8%.
Time spent in licensing: elapsed = 31.9 ms.
Peak memory used = 38.1 Mbytes.
Simulation started at: 12:30:29 AM, Sun Apr 9, 2017, ended at: 12:30:30 AM, Sun Apr 9, 2017, with elapsed time (wall clock): 1.22 s.
spectre completes with 2 errors, 4 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.

  • Cancel
Parents
  • tangudubharat
    tangudubharat over 8 years ago
    Thanks for the reply.

    My error has been resolved.

    It was because of missing of 32 bit version glibc-devel package.

    Thanks for assisting
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • tangudubharat
    tangudubharat over 8 years ago
    Thanks for the reply.

    My error has been resolved.

    It was because of missing of 32 bit version glibc-devel package.

    Thanks for assisting
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information