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[ADE XL] Compiling verilog-A module

Seokhyun Jeong

Hi-

 I am having problems in using ADE-XL due to the verilog-A compiling issue. Every time I run simulation,  the simulator re-compiles all the verilog-A blocks in the schematic even though there's no change. This takes a lot of time as single block consumes ~5min to compile. I know that this is not the case for ADE-L. Although I found similar issue that was posted earlier (https://community.cadence.com/cadence_technology_forums/f/38/t/20866), I couldn't get to the linked solution (Solution 11603330) as I didn't have the permission. So, I asked of of University's department staff who had permission to look it up but he said that the page was expired. It would be appreciated if I could get some help with this issue. I am using IC6.1.5-64b.500.9 .

Thanks,

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