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scs files

samer1

Greetings, 

I am new to developing a compact models. I developed a compact model to a device in Verilog-A and I want to add statistical parameters to it. I looked at an older model developed by my group and figured out that the model is a .scs file that calls the verilog-A model. There is also another file that is .cdf that I do not quite understand what it does. Can some ones explain to me how these three files communicate together in a simulation. 

I am using version 616

Simulator: spectre

here is the .scs file:

////////////////////////////////////////////////////////////////////////////////

simulator lang=spectre

inline subckt memr_hfox (p n)
parameters
+ HRS1=1.5e+05 LRS1=1e4
+ VtP=0.75 VtN=-1.0 tswP=1e-08
+ tswN=1e-06 Rinit1=1.5e+05
+ HRS_rt=2e+06 HRS_nm_spr=0.001 THRS_sp=0.001 TLRS_sp=0.001
+ Ttsw_n_sp=0.001 Ttsw_p_sp=0.001 TVtn_sp=0.001 TVtp_sp=0.001
*
* include Verilog-A model for memristor
ahdl_include "/research/seneca/models/memr_hfox_demo.va"
*
* instantiate Verilog-A memristor model
memr_hfox p n memr_hfox HRS=HRS1 LRS=LRS1 Vtp=VtP Vtn=VtN
+ tsw_p=tswP tsw_n=tswN Rinit=Rinit1 HRS_rate=HRS_rt
+ HRS_nom_spr=HRS_nm_spr THRS_sp_rel=THRS_sp TLRS_sp_rel=TLRS_sp
+ Ttsw_n_sp_rel=Ttsw_n_sp Ttsw_p_sp_rel=Ttsw_p_sp TVtn_sp_rel=TVtn_sp
+ TVtp_sp_rel=TVtp_sp
*
* statistical block for this model
* mismatch used to generate random number per instance
statistics {
mismatch {
vary HRS1 dist=gauss std=0.05 percent=yes
vary LRS1 dist=gauss std=0.05 percent=yes
vary VtN dist=gauss std=0.05 percent=yes
vary VtP dist=gauss std=0.05 percent=yes
vary tswN dist=gauss std=0.05 percent=yes
vary tswP dist=gauss std=0.05 percent=yes
}
}
ends memr_hfox

///////////////////////////////////////////////////////////////////////////////////

  • Hi Sherif

    CDF file is not used directly in the netlisting. It is usually created by the pcell developer to quickly update the CDF section of a cell.

    Here is how spectre .scs model file, verilog-A file and CDF works together:

    a. The netlister adds the following line in the netlist:

    I1 net1 net2 net3 myCell paramA=123 paramB=456

    It knows that "myCell" has 3 terminals and also parameters paramA and paramB because it reads CDF "simInfo" section of the cell. Please see "CIW: Tools->CDF->Edit CDF"


    b. During simulation, spectre now expects a description of a cell named "myCell". This should be present in the .scs model file as:

    subckt myCell pin1 pin2 pin3
    ...
    I1 pin1 pin2 pin3 myVerilogaCell ...
    I2 pin1 pin2 cap *some parasitic elements, etc
    ...
    ends

    c. Verilog-A file then provides the final description of the "myVerilogaCell"
    d. Spectre gets all the required information and proceeds with the simulation


    Best regards
    Quek

  • Thank you Quek. Truly appreciate it.
  • Hi Quek. Thanks for you help.

    I am now trying to create an scs file for a model I have. I have the symbol as well as the verilogA file. I want to treat my device like a transistor where I can include the symbol in a schematic and the include the model files in ADE.

    can you help me with that?

    Thanks

  • Hi Sherif

    You can do it as follows:

    a. Assuming that the cellname of your symbol is "ABC" and your verilog-A file looks like this:

    module ABC(pin1,pin2, ...)
    ...

    b. In library manager, go to "File->New->Cellview" and create a "verilog-A" cellview
    c. Copy and paste the verilog-A codes into the editor
    d. Save and exit

    e. In CIW, go to "Tools->CDF->Edit CDF"
    f. Set the mode to "Base" and select your cell
    g. Change to "Simulation Information" tab
    h. Set simulator as "spectre"
    i. In "instParameters", add the parameters to be netlisted for the verilog-A module
    j. In "termOrder", add the required terminal order as shown in the verilog-A file
    k. In "componentName", add "ABC"
    l. Press OK

    m. You can now use the symbol "ABC" in your schematic


    Best regards
    Quek

  • Quek,

    I hate to be picky, but if you do steps b-d, you don't need to do steps e-l. When you create a verilog-a view it parses the veriloga and creates view-specific CDF automatically for you.

    Regards,

    Andrew.

  • Hi Andrew

    Thanks for the correction. : )

    Best regards
    Quek

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