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Schematic export

askar

Hi,

I want to export my digital design schematic in one process to another process in Cadence Virtuoso.

I export the schematic in verilog or EDIF.

When ı try to export and import the design in EDIF format the schematic is much more preserved. However I need to make changes in the EDIF file to make the import tool understand which is the equivalent cell in the final library. For example a D flip flop in the exported library will have a different equivalent in the imported library. Is there a quick way to make it automatic?

When I try to import the verilog export the schematic equivalent has different routing and symbol views and I cannot import some cells as they are because they lack of definition, they only have verilog file.

Could you please help me carry my design to another process library preserving the schematic view, symbols and connections?

Best,

HIDIR

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  • Andrew Beckett

    Doing this kind of migration via EDIF or (even worse) Verilog is a good way of losing information and complicating matters.

    I have posted some code to help with doing this kind of migration - such as in this post. However, it may be difficult if the symbols don't match.

    Probably best to talk to customer support about this so we can help assess your precise needs.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    Doing this kind of migration via EDIF or (even worse) Verilog is a good way of losing information and complicating matters.

    I have posted some code to help with doing this kind of migration - such as in this post. However, it may be difficult if the symbols don't match.

    Probably best to talk to customer support about this so we can help assess your precise needs.

    Regards,

    Andrew.

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