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scs file calls a verilogA

samer1

Hello, 

I have a ".scs" file that calls a verilogA model. the line in the .scs file that does this reads the following:

memr_TMO_test p n memr_TMO_test HRS=HRS1 LRS=LRS1 Vtp=VtP Vtn=VtN

the verilogA model is called: memr_TMO_test.va 

when I run the simulation in ADE, I get the following error:

/research/seneca/freepdk/memr_TMO_test.scs" 16: Instance `memr_TMO_test' in subckt `memr_TMO_test' recursively calls subckt `memr_TMO_test'. `memr_TMO_test' should be updated to remove the call to `memr_TMO_test'.

can someone help with that

thanks

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  • Andrew Beckett

    You didn't really provide the whole details, but this is telling you that you have a recursive definition. Something like this:

    subckt blob (p n)
    parameters r=1k

    blob (p n) blob r=r

    ends blob

    Unsurprisingly it thinks you have a circular reference. If you really need the subckt name to be the same as the thing being instantiated inside (the Verilog-A module) then you have to add the ahdl_include for the Verilog-A inside the subckt:

    // recurse.scs

    subckt blob (p n)
    parameters r=1k

    // if re-instantiating the veriloga module with the same
    // name, that must be defined within this scope - hence the ahdl_include
    blob (p n) blob r=r

    ahdl_include "recurse.va"

    ends blob

    R1 (n1 0) blob r=2k
    V1 (n1 0) vsource dc=1

    dc dc

    The verilog-A module I used in this example:

    // recurse.va
    `include "disciplines.vams"
    module blob (p,n);
    inout p,n;
    electrical p,n;

    parameter real r=1k;

    analog
      V(p,n) <+ r*I(p,n);

    endmodule

    This works fine.

    Andrew.

Reply
  • Andrew Beckett

    You didn't really provide the whole details, but this is telling you that you have a recursive definition. Something like this:

    subckt blob (p n)
    parameters r=1k

    blob (p n) blob r=r

    ends blob

    Unsurprisingly it thinks you have a circular reference. If you really need the subckt name to be the same as the thing being instantiated inside (the Verilog-A module) then you have to add the ahdl_include for the Verilog-A inside the subckt:

    // recurse.scs

    subckt blob (p n)
    parameters r=1k

    // if re-instantiating the veriloga module with the same
    // name, that must be defined within this scope - hence the ahdl_include
    blob (p n) blob r=r

    ahdl_include "recurse.va"

    ends blob

    R1 (n1 0) blob r=2k
    V1 (n1 0) vsource dc=1

    dc dc

    The verilog-A module I used in this example:

    // recurse.va
    `include "disciplines.vams"
    module blob (p,n);
    inout p,n;
    electrical p,n;

    parameter real r=1k;

    analog
      V(p,n) <+ r*I(p,n);

    endmodule

    This works fine.

    Andrew.

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