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LVS without schematic

Julien Terrier

Hello,

I'm working on cadence virtuso Layout L or XL

Cadence version ==> cadence/ic/06.16.050

Calibre version ==> mentor/calibre/2017.1_25.22

I do only layout, I' drawing only elementary structure such as MOS or CAPA so on then these structure wiil be electrically characterized. Therefor, you can understand, I don't do schematic.

I did any check on my layout as Design Rules Check (here all is perfect).

 Then  we are using Layout versus Schematic to check a short/node between different layer ( Ex : Metal1 (layer) pintext (purpose) and Metal2 (layer) pintext(purpose)), let's have few minutes to details this operation.

We assume  that a semiconductor wafer includes a plurality of chip areas having circuit elements, a scribe line area for defining the chip areas, and a plurality of test element group (TEG) modules

The TEG modules are group formed on the scribe line area. Each of the TEG modules has test transistors, a common source pad, and a common body pad.

A global gate pad is commonly connected to gates of test transistors in the test element group modules.

Global drain pads are shared by respective test transistors in the TEG modules.

So to check the right connection between my PADS and the Gates, Source and drain (i.e physic connection for example metal connection), on one side we put the label (label = pintext) on the gate and on the other side we put a label on the pad, we repeat this operation for the source and the drain.

We are using LVS tools to retrieve a report about connection, we check the report to see whether label gate is connected with label Pad or not in other words we check if there is a short.

Now my issue with this method, I can't be able to detect a "right short" from "wrong short" , sometimes I layout complex structure with lot of connection and in my lvs.report several node results are shaked in one paragraph/section, this makes the analysis difficult.

Hereinafter an example of LVS with "right short" ( no complex structure ;) ):

 

Here in my extraction results I can see that my diode is connected with the PAD1 and the bulk is connected with the PAD2.

 

Hereinafter an example of LVS with "right and wrong short" ( no complex structure ;) ):

Here in my extraction results I can see that my diode is connected with the PAD1 and PAD2 and the bulk is connected with the PAD1 and PAD2.

In this case it's easy to detect the problem but when the structure is more complexe it's very complicated...

We know that LVS tools is not suited for this task and I 'm working on another method more safety but maybe you know a better solution ?

Thank you.

  • Andrew Beckett

    Given that this is a Cadence forum, asking about a flow based around a Mentor tool is probably not the best place to ask it - you should ask in a Mentor forum.

    I suspect that maybe a tool such as PERC (Programmable Electrical Rule Check) may be a better type of tool for the kind of checks you want. Cadence PVS provides a PERC capability, as does Calibre.

    I'm not an expert in PERC but from a high level it might be a better fit than trying to use the connectivity extraction part of LVS to do this without any schematic...

    Regards,

    Andrew.

  • Julien Terrier

    Thank you for your answer, I have send a message to mentor. I didn't find a forum to explain my issue. About PERC is also managing by mentor?

  • Andrew Beckett

    Cadence has a PERC tool (PVS PERC), but I also believe Mentor has one too.

    Regards,

    Andrew.

  • Julien Terrier

    Sorry but I can't find PERC tool in virtuoso Layout L or XL?

    Then I would like create aschematic from my layout I found some explication by using a spice file , I know generate a spice file from my layout with verification tool as lvs and after I don't know to use this spice file to generate a schematic, could you help me?

     

    Regards

  • Julien Terrier
    For my second question I found a partial answer (of you):
    Srinivasa,

    Why would you want to write a SKILL program to do this? Both File->Import->Verilog and File->Import->SPICE (IC61) or File->Import->CDL (IC5141) will do this for you from different netlist formats.

    It seems a bit unnecessary reinventing a standard capability...

    Regards,

    Andrew.
  • Andrew Beckett
    For your PERC question please contact customer support. It's not part of Layout L or XL...

    Andrew.
  • Julien Terrier

    Ok, other thing, what is your piece of advise if I want get a spice file from an XlS, could you give the way if it's possible ?

    for example my file could be build like this:

     

    So drain would be connect to pad 1,  source to pad 6, gate to pad 5 and bulk to pad 7.

    From this features (xls files I think it's the most appropriate form) I would like create a spice file to generate a  Virtuoso Schematic view and finally compare my Layout with my Schematic.

  • Andrew Beckett

    You'd have to write some SKILL code to do this; there's no built-in feature to do table-based schematic generation such as you describe. Probably you'd convert the spreadsheet to CSV, which is easy enough to read in SKILL, and then you'd have to write some code to build the schematic.

    Regards,

    Andrew.

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