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How to determine Scaled-sigma sampling (SSS) Number in high-yield estimation (HYE) for SRAM design? Thanks

Tina Zhao

I am running high-yield estimation (HYE) simulation for custom SRAM design in Virtuoso 6.1.6 ADE XL. The simulation circuit is a critical path which contains representative cells and wire delay models to mimic 512Mb SRAM macro. We do not run a simulation directly on the 512Mb SRAM macro to avoid highly long run-time. 

In HYE setup, we need to specify the sampling number for Scaled-sigma sampling (SSS) method. According to Cadence technical paper, the default number of samples for SSS is 7000. 

The problem is, the 512Mb SRAM macro has millions of devices while the critical path has only hundreds of devices. When we run HYE on the critical path, we expect that the hundreds of devices' variations could mimic millions of devices' variations in some way. Assume that the default 7000 sampling number is appropriate for 512Mb SRAM macro's HYE simulation,  then what sampling number is adequate for  the critical path HYE simulation in order to mimic millions of devices' variations?  

Actually, I am not even sure if the default 7000 sampling number is adequate when running HYE simulation directly on the 512Mb SRAM macro.

I appreciate any suggestions on this problem. Thanks and regards.

  • 7000 should be OK as far as I know - it's the scaled sigma method that supports the extension to high yield, and shouldn't need more samples.

    However, I'll try to get a more precise answer from R&D.

    Regards,

    Andrew.

  • Hi Andrew,

    Thank you for your reply.

    Our most concern is, we use the HYE results of the critical path to predict the yield of the 512Mb SRAM macro. The critical path is composed of hundreds of devices while the 512Mb SRAM macro contains millions of devices. we need to make the hundreds of devices' variation space cover millions of devices' variation space in SSS sampling. Intuitively, if 7000 sampling number is OK for the 512Mb SRAM macro, it seems that the sampling number should increase for the critical path. I am not sure.

    Looking forward to your reply. Have a nice day!

    Tina

  • You might also be interested in the article at http://www.deepchip.com/items/0575-02.html where different approaches to HYE and their possible problems are examined.

  • Thank you for providing useful information.

  • Some comments from Cadence R&D on this:

    The motivation of high yield estimation for memory design is that it is challenging to run full memory module simulation. If users can run 3-sigma Monte Carlo for full memory module, there is no need to apply high yield analysis. This is not possible even applying fast simulator technology.

    Assuming memory cell or path are kind of independent of each other, designers will require memory cell has 6 sigma yield requirements in 1M module. Users typically run high yield for critical path as well. The yield requirement for critical path will be decided approximately how many critical paths can represent the memory module.

    SSS algorithm’s accuracy is not depending on size of circuit. So 7000 is OK to apply to critical memory path.

    Regards,

    Andrew.

  • Hi Andrew,

    Many thanks for your patient replies.

    It may be reasonable to use 7000 SSS points applied to memory critical path to get a high-sigma estimation.

    But still, the difficulty lies in that how to mapping the yield of critical path to that of the full memory module. In other words, in Monte Carlo simulation, if the critical path cannot be extended to 'look like' the full memory module in some way, we have no confidence to say the full memory module has 3 or 4 sigma yield even if the critical path has a 6-sigma yield.

    Regards,
    Tina

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