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  3. VLS-XL Assign instance pin to net - automatically create...

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VLS-XL Assign instance pin to net - automatically create net on clicked target?

caver456
caver456 over 8 years ago

For this case, we are starting with a layout mostly done in L that has pcells but has no nets at all.

In XL, when using Connectivity -> Nets -> Assign to assign an instance pin to a net, the desired target (i.e. the second thing that it prompts you to click) is a shape or another instance terminal that has no net.  In other words, "we want to connect this pin on this pcell resistor to this other simple connectivity-free piece of metal over here."  Apparently, in the Assign command, the target has to be (a shape or via on) an existing net.

While VLS does make it easy to assign a net to the target before running Assign (set the net property on the target shape/via, or add a label and Extract Layout, etc), in this case, we don't really care what VLS thinks the net name is - we just want to see the flight and drag lines.

Is there a way to have Assign automatically create an arbitrary net with a unique net name on the clicked target, which would get rid of the need to take steps to make sure the target is a net before running Assign?

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  • caver456
    caver456 over 8 years ago
    I've got to agree that this limited case would probably not be a compelling enough reason for Cadence to bring this feature back - would we be the first and only to mention it, or, are you looking for more votes to help decide whether it's worthwhile? If it turns out to be something we use a lot, Marc's suggestions will probably work out nicely.

    The instance pins are not yet touching the floating shapes - the goal is to see flight and drag lines between the two disjoint items, so, it doesn't sound like Propagate would be a fit there. So far I've been using two methods to create new nets: 1) add a label somewhere on the floating shape or something already connected to it, then extract layout with Layout XL Options -> Connectivity -> Controls -> Connectivity Assignment -> Assign shapes from attached labels checked; and 2) edit a floating shape and give it a (new, unique) net name directly. Basically we go with option 1) where we've already drawn labels during the VLS-L layout process, and option 2) elsewhere. Keeping the Navigator open and viewing the list of nets is a good way to make sure you can pick a unique net name; I've just been going with the alphabet but zero-padded numbers would probably work better for viewing in the navigator.

    The schematics we use are not from Cadence, so, we use a CDL-like spice-like netlist to LVS against and that's really the only "connectivity source" we have to go from. As far as VLS-XL goes, there is no connectivity source. I've messed with SpiceIn a bit, and gotten it to work a few times for small test cases, but massaging our netlists to be fully usable by SpiceIn may not be an effective use of time. We've got some SKILL code to do a limited equivalent of "Generate all from source" by reading the netlist, and it's been a big help so far, but this was built for VLS-L and does not yet do connectivity - just devices. Now that we may have more access to XL for the long term, we'll probably try to add connectivity generation to that code.

    Still, that code enhancement would address the case where we are starting a new cell, with an existing CDL as the "source". What we're really looking for here is a workflow to address the mid-stream case, where a lot of layout work has been done using VLS-L in a given cell (i.e. all the fets) and we want to use the flight lines and drag lines in VLS-XL for the remainder of the layout (analog devices, blocks, etc).
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  • caver456
    caver456 over 8 years ago
    I've got to agree that this limited case would probably not be a compelling enough reason for Cadence to bring this feature back - would we be the first and only to mention it, or, are you looking for more votes to help decide whether it's worthwhile? If it turns out to be something we use a lot, Marc's suggestions will probably work out nicely.

    The instance pins are not yet touching the floating shapes - the goal is to see flight and drag lines between the two disjoint items, so, it doesn't sound like Propagate would be a fit there. So far I've been using two methods to create new nets: 1) add a label somewhere on the floating shape or something already connected to it, then extract layout with Layout XL Options -> Connectivity -> Controls -> Connectivity Assignment -> Assign shapes from attached labels checked; and 2) edit a floating shape and give it a (new, unique) net name directly. Basically we go with option 1) where we've already drawn labels during the VLS-L layout process, and option 2) elsewhere. Keeping the Navigator open and viewing the list of nets is a good way to make sure you can pick a unique net name; I've just been going with the alphabet but zero-padded numbers would probably work better for viewing in the navigator.

    The schematics we use are not from Cadence, so, we use a CDL-like spice-like netlist to LVS against and that's really the only "connectivity source" we have to go from. As far as VLS-XL goes, there is no connectivity source. I've messed with SpiceIn a bit, and gotten it to work a few times for small test cases, but massaging our netlists to be fully usable by SpiceIn may not be an effective use of time. We've got some SKILL code to do a limited equivalent of "Generate all from source" by reading the netlist, and it's been a big help so far, but this was built for VLS-L and does not yet do connectivity - just devices. Now that we may have more access to XL for the long term, we'll probably try to add connectivity generation to that code.

    Still, that code enhancement would address the case where we are starting a new cell, with an existing CDL as the "source". What we're really looking for here is a workflow to address the mid-stream case, where a lot of layout work has been done using VLS-L in a given cell (i.e. all the fets) and we want to use the flight lines and drag lines in VLS-XL for the remainder of the layout (analog devices, blocks, etc).
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