Dynamically Changing the pulse width - vpulse/vsource

Vijay,

It rather depends on what you want to vary and what the condition is. If it's a simple event - when something reaches a limit you want to change the pulse width - then you can do that in SPECTRE17.1 using something like this:

parameters pulsewid=20n
Vramp (ramp 0) vsource type=pulse val0=0 val1=2 rise=1u
whenHigh assert expr=V(ramp) min=0 max=1.2
Vpulse (outpulse 0) vsource type=pulse val0=0 val1=1 period=100n width=pulsewid rise=1n fall=1n

tran tran stop=1u param=pulsewid param_vec=[0 20n @whenHigh 70n]

This means that the parameter pulsewid will change when the assert whenHigh fires. It only happens the first time - and the value you change it to is fixed. You can do all this from the ADE UI (I purposefully didn't use the dev=Vpulse on the tran line to vary the instance parameter width on the pulse source because you'd have to add the Additional parameter dev=Vpulse on the tran options form to do this as it doesn't appear on the UI; so instead I use a design variable to control the pulse width).

I suspect you want the pulse width to be more continuously variable (e.g. some kind of PWM waveform). In which case, you'd need to write a Verilog-A model for the pulse generator - that would be the easiest way by far.

Regards,

Andrew.

Vijay,

It rather depends on what you want to vary and what the condition is. If it's a simple event - when something reaches a limit you want to change the pulse width - then you can do that in SPECTRE17.1 using something like this:

parameters pulsewid=20n
Vramp (ramp 0) vsource type=pulse val0=0 val1=2 rise=1u
whenHigh assert expr=V(ramp) min=0 max=1.2
Vpulse (outpulse 0) vsource type=pulse val0=0 val1=1 period=100n width=pulsewid rise=1n fall=1n

tran tran stop=1u param=pulsewid param_vec=[0 20n @whenHigh 70n]

This means that the parameter pulsewid will change when the assert whenHigh fires. It only happens the first time - and the value you change it to is fixed. You can do all this from the ADE UI (I purposefully didn't use the dev=Vpulse on the tran line to vary the instance parameter width on the pulse source because you'd have to add the Additional parameter dev=Vpulse on the tran options form to do this as it doesn't appear on the UI; so instead I use a design variable to control the pulse width).

I suspect you want the pulse width to be more continuously variable (e.g. some kind of PWM waveform). In which case, you'd need to write a Verilog-A model for the pulse generator - that would be the easiest way by far.

Regards,

Andrew.

Thanks Andrew for your detailed reply. As you suspected, I want to have something like pulse width waveform. So as per your suggestion, I will develop Verilog-A model for PWM. Please provide some references (if any) for PWM verilog-A model.

But I really salute your replies in the forum. You are not just responding to the question, you are going one step ahead, visualize the expectations of the thread and providing possible avenues for the solution.

Once again thanks Andrew.

Regards,

Vijay.

Vijay,

Here's how I did it - I have a triangle wave at the clock rate, and then compare the signal with the triangle wave - and the Verilog-A is there just to generate the well-formed pulses at the crossing points of the comparator - effectively the Verilog-A model is just a comparator, really. 

I'm showing a netlist and the model (the netlist is easier to grasp than a picture of the schematic where you can't see all the parameters).

//
I1 (pwmout 0 sig 0 triangle 0) PWM
Vsig (sig 0) vsource type=sine freq=1k ampl=0.5 dc=1
Vtri (triangle 0) vsource type=pulse val0=0.2 val1=1.8 rise=0.5u \
fall=0.5u width=0 period=1u

ahdl_include "forumpwm.va"

tran tran stop=1m

Here's the Verilog-A:

`include "disciplines.vams"
module PWM (outp,outn,sigp,sign,trip,trin);
input sigp,sign,trip,trin;
electrical sigp,sign,trip,trin;
output outp,outn;
electrical outp,outn;

parameter real risefall=1n;
parameter real low=0;
parameter real high=1.0;
real level;

analog begin
  @(cross(V(sigp,sign)-V(trip,trin)));
  level=V(sigp,sign)>V(trip,trin)*(high-low)+low;

  V(outp,outn) <+ transition(level,0,risefall);
end

endmodule

Regards,

Andrew.

Thank you very much Andrew for your efforts and time.

Really cadence forum is very effective in addressing issues or questions on IC design. Your replies are more helpful for the young researchers like me. Thanks Andrew.

Regards,

Vijay