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VNCAP error

EngrZM

hi 

i am using virtuoso layout suite (v IC6.1.5.500.16.2). While using the vncap form technology library of 65nm CMOS; i am getting following error:

" adjacent (interdigitated) Mx or By fingers must be on different nets.

 where x=1-6 and y=1,2,A,B "

actually this capacitor is being used as a matching capacitor between two differential nodes of balun output (custom made). Therefore both end of cap are referring to same net. 

It can be solved by splitting cap and making differential but want to know about the solution in case when this splitting is not possible. 

thanks

zubair

  • Andrew Beckett

    This is a question about the specific technology you're using - not the tool itself. Given that you didn't say which technology you're using, it's going to be difficult for anyone to answer - even then, it might be tricky for folks to answer in a public forum without breaking NDAs on the technology (as it's not from Cadence but from the foundry themselves).

    You'd probably be best advised to ask this to the PDK supplier (probably the foundry supplying the 65nm technology you're using).

    Regards,

    Andrew.

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