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Simulation with verilog-a model

HANNN

I am trying to simulate a memristor model and check basic operations.

I got memristor source code written with verilog-a(below).

module memristor (p, n) ;

inout p, n ;
electrical p, n ;

parameter real uv = 10f;
parameter real d = 10n;
parameter real ron = 100;
parameter real roff = 38k;
parameter real rin = 5k;

real k, r1, r2, R;


analog begin

k = 2 * uv * ron * (roff - ron) / pow(d,2);
r1 = pow(rin,2) + k * idt( V(p,n), 0 );
r2 = min( pow(roff,2) , max(r1,pow(ron,2) ) );
R = sqrt(r2);
V(p,n) <+ R * I(p,n) ;

end

endmodule

And I created a cellview to add sin wave voltage source like below.

But when I simulated above module with ADE XL, Result is 

Memristor has a constant resistance rin(of above code).

I think idt(...) of the code does not work. Should I do something more when simulate with verilog-a module? 

Thank you.

  • Andrew Beckett

    I'm not that familiar with memristors (other than the odd article I've read on them) and so I didn't check to see whether the model you gave made sense. However, I can see that the idt is definitely working. If I do:

    //

    M1 (pos 0) memristor
    V1 (pos 0) vsource type=sine ampl=1 freq=1k

    ahdl_include "forummemristor.va"

    myopts options saveahdlvars=all
    tran tran stop=2m

    I can then plot the voltage across the memristor and the value of r1 (which includes the integral of the voltage across the device) - you can see from this that the integral is working:

    Regards,

    Andrew.

  • HANNN
    in reply to Andrew Beckett

    Thank you for your answer Andrew.

    However, I think I did same with you but value of r1 does not vary in my simulation. 

    also, this is my netlist. 

    ----------------------------------------------------------------------------------------------------

    // Generated for: spectre
    // Generated on: Jan 9 15:49:15 2018
    // Design library name: MCA
    // Design cell name: test
    // Design view name: schematic
    simulator lang=spectre
    global 0

    // Library name: MCA
    // Cell name: test
    // View name: schematic
    I2 (Pos GND) memristor uv=1e-14 d=1e-08 ron=100 roff=38000 rin=5000
    V0 (GND 0) vsource dc=0 type=dc
    V3 (Pos 0) vsource dc=0 type=sine ampl=1.5 freq=500M
    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
    tran tran stop=100n write="spectre.ic" writefinal="spectre.fc" \
    annotate=status maxiters=5
    finalTimeOP info what=oppoint where=rawfile
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts where=rawfile
    save I2:p
    saveOptions options save=allpub saveahdlvars=all
    ahdl_include "/home/kkh4969/65nm/MCA/memristor/veriloga/veriloga.va"

    ----------------------------------------------------------------------------------------------------

    Sorry, I am beginner in designing circuit. If you find something wrong, please tell me. Thank you.

  • Andrew Beckett
    in reply to HANNN

    It's because the magnitude of the integral part is tiny in your example because of the higher frequency of the sine wave. If you plot just I2:r1 (and not I2:R on the same graph) you'll still see the sinusoidal variation and it has the correct phase relationship with the input voltage to show it's an integral. However, the integral is only 1n peak to peak, whereas in my example (with 1kHz rather than 500MHz) it has ~300u peak to peak.  So the idt is very small variation on top of the 25M value that comes from rin in the equation for r1.

    Andrew.

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