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Assura LVS Parameter Mismatch Error

tonyinbos

Hi All,

I'm using Virtuoso Layout XL 617 and Assura 415, with TSMC mixed-mode 130nm PDK.

I included a multi-fingered NMOS moscap into the layout, using the generated parameterized cell. The Cap has 5 fingers, W=L=20um for each, with top&bottom plate connection, and top poly contact head.

 

The cell looked like that above.

However, when running assura lvs, I got the following error:

Schematic Instance: C0 nmos1v
Layout Instance: avD10_1 N

w 2e-05 vs 0.0001 differs by 400%
Layout Instance is the merged result of: avD10_1 avD10_2 avD10_3 avD10_14
avD10_15

While clearly the device has five fingers totaling 100um, ASSURA says it's only 20um. It works only when just 1 finger is used. Is there an explanation to this weird behavior of ASSURA? Thank you very much. -Tony

Parents

  • It's unlikely to be Assura's fault - it's probably the rule deck (or the rule deck not being used properly). This is something that you either need to take up with the foundry (TSMC) or maybe as a first step Cadence Customer Support - that way we can look at the exact situation  you have - and retrieve the rule deck for the specific document number you have (there are several 130nm processes, so we'd need to check the right one) and check what's going on.

    Regards,

    Andrew.

Reply

  • It's unlikely to be Assura's fault - it's probably the rule deck (or the rule deck not being used properly). This is something that you either need to take up with the foundry (TSMC) or maybe as a first step Cadence Customer Support - that way we can look at the exact situation  you have - and retrieve the rule deck for the specific document number you have (there are several 130nm processes, so we'd need to check the right one) and check what's going on.

    Regards,

    Andrew.

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