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  3. Assura LVS Parameter Mismatch Error

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Assura LVS Parameter Mismatch Error

tonyinbos
tonyinbos over 7 years ago

Hi All,

I'm using Virtuoso Layout XL 617 and Assura 415, with TSMC mixed-mode 130nm PDK.

I included a multi-fingered NMOS moscap into the layout, using the generated parameterized cell. The Cap has 5 fingers, W=L=20um for each, with top&bottom plate connection, and top poly contact head.

 

The cell looked like that above.

However, when running assura lvs, I got the following error:

Schematic Instance: C0 nmos1v
Layout Instance: avD10_1 N

w 2e-05 vs 0.0001 differs by 400%
Layout Instance is the merged result of: avD10_1 avD10_2 avD10_3 avD10_14
avD10_15

While clearly the device has five fingers totaling 100um, ASSURA says it's only 20um. It works only when just 1 finger is used. Is there an explanation to this weird behavior of ASSURA? Thank you very much. -Tony

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  • Budlah IC
    Budlah IC over 7 years ago

    Tony,

    When you say it only works when just 1 finger is used, do you mean just 1 finger in the layout?  If so, then have a look at the netlist on the schematic side. Since you said it was a generated pcell, I assume you are using XL and the schem device has fingers=5. If still so, then it sounds like your schematic is not netlisting correctly within Assura.  (assuming you are netlisting through Assura)  We are seeing something similar, using Assura in a completely different PDK, different process, different fab, and in 6.17.  Our netlists on the schematic side don't correctly reflect some of the parameters (such as numberOfFingers or multiplier) as defined in the schem, so we see similar parameter errors.  Not blaming Cadence for this, but we haven't figured it out yet.  If you can't get past this,  2 possible workarounds, until the real problem is determined, are:  1) try creating a CDL netlist first and reference that in your LVS run, or 2) consider requesting that the parameters of the schematic device be changed such that numberOfFingers is changed from 5 to 1, while either the multiplier is changed from 1 to 5, OR the instance is arrayed <5::0>.  When you (re) generate the layout device you will get 5 individual units rather than one 5-finger unit and will have to overlap the S/D's yourself - no big deal - and you might find better LVS results.  Good luck.

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  • Budlah IC
    Budlah IC over 7 years ago

    Tony,

    When you say it only works when just 1 finger is used, do you mean just 1 finger in the layout?  If so, then have a look at the netlist on the schematic side. Since you said it was a generated pcell, I assume you are using XL and the schem device has fingers=5. If still so, then it sounds like your schematic is not netlisting correctly within Assura.  (assuming you are netlisting through Assura)  We are seeing something similar, using Assura in a completely different PDK, different process, different fab, and in 6.17.  Our netlists on the schematic side don't correctly reflect some of the parameters (such as numberOfFingers or multiplier) as defined in the schem, so we see similar parameter errors.  Not blaming Cadence for this, but we haven't figured it out yet.  If you can't get past this,  2 possible workarounds, until the real problem is determined, are:  1) try creating a CDL netlist first and reference that in your LVS run, or 2) consider requesting that the parameters of the schematic device be changed such that numberOfFingers is changed from 5 to 1, while either the multiplier is changed from 1 to 5, OR the instance is arrayed <5::0>.  When you (re) generate the layout device you will get 5 individual units rather than one 5-finger unit and will have to overlap the S/D's yourself - no big deal - and you might find better LVS results.  Good luck.

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