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Assura LVS Parameter Mismatch Error

tonyinbos

Hi All,

I'm using Virtuoso Layout XL 617 and Assura 415, with TSMC mixed-mode 130nm PDK.

I included a multi-fingered NMOS moscap into the layout, using the generated parameterized cell. The Cap has 5 fingers, W=L=20um for each, with top&bottom plate connection, and top poly contact head.

 

The cell looked like that above.

However, when running assura lvs, I got the following error:

Schematic Instance: C0 nmos1v
Layout Instance: avD10_1 N

w 2e-05 vs 0.0001 differs by 400%
Layout Instance is the merged result of: avD10_1 avD10_2 avD10_3 avD10_14
avD10_15

While clearly the device has five fingers totaling 100um, ASSURA says it's only 20um. It works only when just 1 finger is used. Is there an explanation to this weird behavior of ASSURA? Thank you very much. -Tony

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  • To clarify, I tend to agree with Andrew in that it is not likely Assura, but perhaps the deck, which points at the PDK and thus the foundry.  That is our suspicion for our own issues as well, but at this point that is only a guess.  In the meantime we look for workarounds so we can keep cranking.  The alternative methods I mentioned have been successful for that.

  • in reply to Budlah IC

    Hi Budlah and Andrew,

    Thank you very much for your reply and suggestions.

    Like Budlah said, "Just 1 finger" means only 1 finger in the layout.

    I'm using ASSURA DFII. But I'm not very familiar with how ASSURA works, so I'm not sure if that means I'm netlisting through ASSURA.

    I tried changing multiplier in the device properties in schematics, but somehow that didn't work, ASSURA still gives the same LVS error.

    However, renaming the device name to <0:4>, basically like doing a manual multiplier in schematics, and then re-overlapping it in the layout, and it worked, on the exact same-looking layout!

    That only solved part of my problem though, as I encountered a new LVS parameter mismatch error on a MiM cap. It says 

    Schematic Instance: C0 mimcap
    Layout Instance: avD90_1 mimcap_1p0_sin

    c 4.99952e-12 vs 3.34349e-12 differs by 33.1238%
    Layout Instance is the merged result of: avD90_1 avD90_2 avD90_3 avD90_4

    While all I did is to route an auto-generated MiM cap cell in the layout.

    Shall I open a new thread with this?

    Many thanks again to both of you.

    -Tony

  • in reply to tonyinbos

    Again, this new issue is specific to the technology you're using - and also might be related to what you've done in the layout. It's unlikely we can provide much help in the forums without being able to see more - so I'd suggest contacting the foundry or maybe customer support, as I suggested before.

    Regards,

    Andrew.

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  • in reply to tonyinbos

    Again, this new issue is specific to the technology you're using - and also might be related to what you've done in the layout. It's unlikely we can provide much help in the forums without being able to see more - so I'd suggest contacting the foundry or maybe customer support, as I suggested before.

    Regards,

    Andrew.

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