Assura LVS Parameter Mismatch Error

Hi Tony,

Did you solve your problem? If yes, how did you do it?

I am facing almost the same problem. I have an inductor in my design. While its spacing is 4 um both in schematic and layout, LVS report sees it as ~1um. When I go layout and measure its spacing manually, it is indeed 4 um. This problem had occurred once again for simple MOS transistors. While they had 4 fingers, LVS reported that they have 8 fingers. For the MOS case, I found a workaround by chainging the number of fingers of MOS in schematic keeping the total width/length. But for the inductor, the pdk does not allow me to give a spacing value less than 2 um.

Do you have any suggestion for me?

I am using Cadence Virtuoso 6.1.3 and Assura 6.1.3.. My netlist type is DFII and the pdk that I am using is HHNEC 0.18um.

Thank you for any kind of help in advance.

Kind regards,
M.Ali

Hi Ali,

It's been a while so I don't remember every detail of the problem. If I remembered correctly - it seemed to be an issue with the LVS schematic extraction, and I followed Budlah's advice, avoiding the use of multi-fingered instances and instead use <0:n> arrayed ones and it worked out fine.

Specific to the problem you're facing, does LVS work with a schematic & layout with only the inductor instance? If it's still problematic, then I would suggest either try using a different inductor option, or carefully simulate the physical layout, ensuring it connects to where it should connect to and works as it should work, then check off the error with the foundry (basically living with the error and waiving your rights to complain if the taped out chip didn't work, do allow for ample time to communicate!).

Good luck and best,

Tony

Hi Tony,

Thank you for turning me back.

I checked LVS with a schematic&layout with only the inductor. Still, it's problematic. But I would like to mention couple of strange things about this LVS issue.  

1) For example, if I change the parameters of inductor (both in schematic and layout) I might get clear LVS result. As I mentioned in my previous post, inductor spacing was 4 um (which is max allowed for spacing). Interestingly, when I change another parameter of inductor, this spacing value could jump up to 4.04 um, which is higher than the max, automatically and Virtuoso doesn't force it to be 4 um. If I attempt to change spacing to 4.04 um manually without changing the other parameter, Virtuoso doesn't allow me. And when it is 4.04 um, I am able to pass LVS test.

2) Without changing anything else, when I intentionally change pin labels to 'drawing(drw)' purpose (not 'text(tt)' purpose), I got a 'Pin Mismatch' error, which is as expected. But I don't get a parameter mismatch error while nothing is different with the previous case.

3) One of my labmates was using the same pdk. He was getting this strange 'parameter mismatch error', too. He updated the pdk and used ' CDB to OpenAccess Translator ' ( one of the toolboxes of Virtuoso ) and converted his  cds.lib a nd he passed LVS, without getting errors but warnings. I followed the same method and it didn't work for me.

4) In this parameter mismatch error, I had said while actual spacing was 4 um, LVS report sees it ~1 um. I changed the spacing to 2 um (both in schematic&layout) and LVS report saw it ~0.5 um, this time.  Plus, I couldn't get what you mean here. Would you please explain it a bit?  

tonyinbos said:

check off the error with the foundry (basically living with the error and waiving your rights to complain if the taped out chip didn't work, do allow for ample time to communicate!)

Kind regards, M.Ali

Hi Tony,

I have somehow found a way. For anyone who has struggled with the same thing, this is thing that I did:

I made the spacing 3.96 um instead of 4 um and LVS worked. I don't know but LVS seems not like integers. This might be a grid problem or something else.

Kind regards,
M.Ali

This is unlikely to be a generic problem with "LVS" - it will be something to do with the specific rules for the specific foundry you're using - it might be an error in the rules or it might be a real issue - you really should check with the foundry as was suggested by Tony.

Andrew.

Yes, we already have asked them and are waiting for the answer..

M.Ali

Yes, we already have asked them and are waiting for the answer..

M.Ali