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How is the netlisting done in ADE

anoopvk

Hello All,

How is the netlisting done generally.

I want to understand for example , an ams netlist will have instantiation of components in Verilog format. From where these ports for the models are picking up.

I can see in the model files for each component there are some parameters like length , width etc. In the netlist these are passed in Verilog format while instantiating that model using "analogmodel".

Thanks in advance

  • Andrew Beckett

    This is a bit of an open-ended question, and it also depends on which netlister choice you’re using for AMS. For the newer UNL (Unified Netlister) it uses a combination of the Verilog netlister and the spectre netlister - and then uses an assembly process to combine (and translate) these into Verilog-AMS. In general hierarchical schematics are netlisted by using information about the pins, nets and instances in the schematic - and then the same pins are used for instances of that block. For leaf level components (i.e. stopping views), information from the CDF of that cell, notably the spectre simulation information, is used to know how to format the instance statement,

    Since you presumably have a more specific issue, it’s probably best to contact customer support so that we can have a look at your data and then give guidances as to what is going on (if there’s an actual issue).

    Regards,

    Andrew.

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