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  3. cadence chip assembly autorouter drc error

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cadence chip assembly autorouter drc error

Supriyo
Supriyo over 7 years ago

Hi,

I am using cadence version IC6.1.6 to design in soi45nm technology. I have a drc rule file to be used with calibre nmDRC but it does not support assura. When I tried to run chip assembly router for automatic routing, there were many drc errors on the finished layout. I am guessing it might be because virtuoso chip assembly router uses default design rule file and therefore not consistent with the rules used by calibre. 

Can anybody offer any insight into this. What should be the approach to convert calibre drc rule set to assura so that I can run assura drc or is there other way to get around this problem. I am also thinking if it would be possible to guide the auto router to use calibre drc rules. 

So far I know that my university does not have assura drc rule file for soi45nm technology. 

Thanks

Supriyo

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  • Andrew Beckett
    Andrew Beckett over 7 years ago

    Hi Supriyo,

    The Chip Assembly Router does not use Assura (or Calibre) rules, so having Assura rules won't fix the problem anyway. It uses information in the OA technology database (in your technology library) to define the minWidths, minSpacings and so on for each layer and interactions with layers. It suggests that maybe your technology library is incomplete - so you either need to contact the foundry who provided the technology database, or go through your university programme. If in Europe that might be Europractice - don't know where you're based.

    Regards.

    Andrew.

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  • Supriyo
    Supriyo over 7 years ago in reply to Andrew Beckett

    Thanks Andrew for the direction. I will see if my university contact can help me go through this.

    Regards

    Supriyo 

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