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not_gate verilogA model in ahdlLib

VLSIiitm

The following lines are in the verilogA model of "not_gate" in ahdlLib. I have marked 3 lines as A, B, C.

@ ( initial_step ) begin
... <<deleted lines>>
end

logic_in = V(vin) > vtrans; // line A

@ (cross(V(vin) - vtrans, 1))  logic_in = 1; // line B
@ (cross(V(vin) - vtrans, -1)) logic_in = 0; // line C

  • What is the reason for having both line A and lines (B,C)? Latter seem to imply the former unless the inputs don't cross the threshold at all during the transient simulation.
  • Would it have been enough to have line A within @(initial_step) begin  ... end?
  • If line A is indeed redundant, does having it slow things down because it is continuously evaluated?

Other gates have similar codes.

Thanks

Nagendra

  • Andrew Beckett

    Nagendra,

    One benefit is that this wouldn't have hidden states for SpectreRF because logic_in is updated on every timestep. Without line A, it would only get recorded on the crossings - so there would be no initial value, and SpectreRF would not be able to simulate it. The @cross is needed to ensure that there is a timestep at the transition.

    I probably would have written it just as:

    @(cross(V(vin)-vtrans)); // force timetep at transition (either direction)
    logic_in=V(vin)>vtrans;

    I don't think it will make any significant difference to the performance.

    Regards,

    Andrew.

  • VLSIiitm
    in reply to Andrew Beckett

    Thanks. Out of curiosity, will pss with initial transient(tstab) look at what is inside @(initial_step) begin ... end?

  • Andrew Beckett
    in reply to VLSIiitm

    Yes, it should do. Note, I didn't actually test this model with pss - this is from visual inspection only...

    Regards,

    Andrew.

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