Verilog-A import variables from file

Wouldn't the simplest thing be to create a file with all the real var_NN=val; lines in, and then include it into your model using `include ?

Otherwise you're still going to need to declare all the variables, even if you did write some code to read the values from a file in an analog initial block (say).

Regards,

Andrew.

Yes, that is exactly what I want to do, I do get an error message from the parser logfile in spectre:

Error found by spectre during AHDL compile.
ERROR (VACOMP-2259): "real<<--? a_vtune_tt_gm1[3:1] = {3.112405e-21, 3.906165e-24, -1.919062e-26};"
"/icd/proj/g6r2/users/uidn5147/svn/pll/octave/vco_param.vams", line 5:
syntax error.

The file "vco_params.vams" looks like this:

// Gear -1 parameter
////////////////////////
//Filename: vcocore_fvco_gear-1.cds.matlab.m
//Corners: top_tt_-40_125
real a_vtune_tt_gm1[3:1] = {3.112405e-21, 3.906165e-24, -1.919062e-26};
real b_vtune_tt_gm1[3:1] = {-1.207183e-10, -1.987258e-13, 2.910812e-16};
real c_vtune_tt_gm1[3:1] = {1.060114e+00, 7.085940e-04, 4.460605e-07};

I do have to questions:

1. What is the required format/syntax for the include file ?

2. How can I open a texteditor in Virtuoso without creating a cellview ?

I suspect (because I can reproduce the errors by doing the same) that you're including the file in the wrong place in the model. Here's a Verilog-A example:

`include "disciplines.vams"

module forum41 (a,b);
inout a,b;
electrical a,b;

`include "forum41inc.va"

analog begin
  V(a,b)<+ c_vtune_tt_gm1[3]*I(a,b);
end

endmodule

And then the forum41inc.va: 

//Corners: top_tt_-40_125
real a_vtune_tt_gm1[3:1] = {3.112405e-21, 3.906165e-24, -1.919062e-26};
real b_vtune_tt_gm1[3:1] = {-1.207183e-10, -1.987258e-13, 2.910812e-16};
real c_vtune_tt_gm1[3:1] = {1.060114e+00, 7.085940e-04, 4.460605e-07};

This works fine. Note that the `include is inside the module - so that the code gets inserted into the right place in the model. I suspect you put the `include outside of the model.

If you're asking about using the Verilog-A or Verilog-AMS editors without a cellView, I think the answer is that you can't... probably the best you could do is create a cellView and put a dummy module at the top and end module at the bottom whilst you create the file so that you get syntax highlighting, and then remove those when you're done.

Note that the syntax is identical to what it would be if the statements were directly in the module - all the `include is doing is preprocessing the file and including everything before the compiler gets to it.

Regards,

Andrew.

Perfect ! Putting the file inside the module does the job.

Now the next question arises:

How can I have this file as a part of my cell, but not being a cellview ?

I would like to see the file in the library browser and have a relative path in the include command.

So far I was using an absolut path - but I see that you gave just the filename - so I am wondering where you saved this file and if you see it in the library browser ?

I first had tested this by running spectre standalone. I've now done it more like you suggested - as follows:

1. Assuming I'm creating mylib/myblock/veriloga
2. Create mylib/myblock/verilogaInc as a "text" view (not as a VerilogA view). In this text view create your variable definitions
3. Then in mylib/myblock/veriloga you can add:
   `include "../verilogaInc/text.txt"

That works with both the checker in Virtuoso - it finds the included file, plus when you run simulation.

Regards,

Andrew.