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  3. saveNetlist option changing view to functional from schematic...

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saveNetlist option changing view to functional from schematic- Innovus to Calibre

kash022
kash022 over 7 years ago

Hello All,

I am performing an LVS run using Calibre. For this, I imported the stream/gds file and the the verilog file after my backend flow (Innovus).  The .v file was converted to a SPICE netlist  (not sure how..but if anyone could explain it a bit would be an additional help!!)

So now coming to the issue at hand,
the LVS was not an absolute match because of the presence of DECAPS which are there in the layout but not in the extracted schematic from the verilog.
So, to resolve this I added the option -includePhysicalCell {string/name of the decap cells} -includePhysicalInst in the saveNetlist option (in Innovus), extracted once again and performed a new LVS run. But now, the problem is that the top level is no longer schematic. It has changed to functional. 
Any ideas how to resolve this issue?
Thanks,
Cheers,
Kashif
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  • Andrew Beckett
    Andrew Beckett over 7 years ago

    Kashif,

    This question appears to be covering a number of different areas - and is not entirely clear because the flow used wasn't really described. Anyway, some points:

    • Issues with Calibre LVS aren't best handled in these forums because Calibre is a Siemens Mentor tool, not a Cadence tool.
      • Note that Calibre has a capability to convert Verilog to CDL (which is a SPICE-like netlist format used for physical verification) - not sure if that's what is being used though.
    • Options related to Innovus would be better asked on the Digital Implementation forum
    • The only Custom IC but here I can see is where you mentioned "the top level is no longer schematic. It has changed to functional". That suggests that maybe you've used File->Import->Verilog in Virtuoso to import the Verilog and create schematics. However, it's not clear from anything else  you've said whether you've done that. Normally it will create functional views if the Verilog contains behavioural constructs (as obviously creating a schematic then becomes impossible). However, I don't know whether this is relevant either, since it's not clear that you used Import Verilog or what you expect to get out of this...

    Regards,

    Andrew.

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  • kash022
    kash022 over 7 years ago in reply to Andrew Beckett

    Hi Andrew,

    Thank you for your reply....and apologies if I erred on the forums...promise to be careful from next time :-)

    You're right about me using File -> Import -> Verilog....the verilog file in this case is the "physical" verilog generated from the innovus backend; so on importing now I see the following warnings in the Virtuoso CIW

    WARNING (VERILOGIN-127): Rejecting library, *******_****_****, cell, ******_DECAP*****, view, symbol, for module, ******_DECAP*****, because port gnd doesnot exist or is not present in the portOrder property.

    WARNING (VERILOGIN-22): Module *******_***DECAP****, instantiated in the top module AES_SBOX_Registers, is not defined. Therefore the top
    module AES_SBOX_Registers will be imported as functional.

    Now, when I navigate to the path for the decap...I see that it just has a symbol..and no definition of any of the ports (just a png oa and tag files)...Any ideas how to resolve this?  Is this a Cadence issue or a PDK related issue?

    Thanks!

    Cheers,
    Kashif

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  • Andrew Beckett
    Andrew Beckett over 7 years ago in reply to kash022

    Hi Kashif,

    It's likely to be an issue with the standard cell library, but the best thing to do would be to contact customer support. I don't think it's going to be terribly easy to diagnose this without seeing the data in more detail.

    Regards,

    Andrew.

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