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Convergence problems using analogLib switch (DC simulation)

netbug

Dear all,

I am doing a simple testbench for a comparator and would like to have several voltage sources, for different type of analysis, but only one common input on the comparator.

So I've defined the name of the comparator's input to be "stimuli" and the voltage sources to be called: sine, pulse and step.

Zoom of the previous figure

I know that the schematic above won't work for many reasons, but I just want to make clear what I would like to do. But even with one switch only, the DC simulation won't converge.

Many thanks.

Best regards,

Pedro

  • Andrew Beckett

    Pedro,

    Please can you post the top level netlist (i.e. all the instances of the relay component and so on) - don't necessarily need to see the rest of the hierarchy (unless you're happy to share them) - would help to see the parameters to the switches.

    Also can you post the output log from the simulator so we can see how it fails to converge.

    Thanks,

    Andrew.

  • netbug
    in reply to Andrew Beckett

    Hi Andrew,

    Thanks for replying.

    I removed all the relays,except one, and it doesn't converge. However, if I put back the other 2, it converges. :-|

    But, when using all the 3 sources, the pulse signal at the input of the comparator is distorted (it seems like it was super imposing the sine wave on the square wave. Playing with the "close switch resistance" (set to 1nohm now, which may be too low) changes a lot the signal shape.

    Please check attached the log file, netlist and a TB screenshot.

    Fullscreen TBcomparator_log.txt Download 
    Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 14.1.0.664.isr9 32bit -- 6 Jun 2015
Copyright (C) 1989-2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: pcardoso   Host: swsrvcomp-18   HostID: 140A121D   PID: 15711
Memory  available: 29.7079 GB  physical: 270.5633 GB
CPU Type:       Intel(R) Xeon(R) CPU E5-2667 v2 @ 3.30GHz
          Processor PhysicalID CoreID Frequency Load
              0         0        1     3300.2     2.5
              1         1        1     3300.2     2.7
              2         0        2     3300.2     2.4
              3         1        2     3300.2     3.0
              4         0        3     3300.2     2.1
              5         1        3     3300.2     2.4
              6         0        4     3300.2     1.8
              7         1        4     3300.2     2.3
              8         0        8     3300.2     1.8
              9         1        8     3300.2     2.4
             10         0        9     3300.2     2.1
             11         1        9     3300.2     2.7
             12         0        10     3300.2     2.3
             13         1        10     3300.2     2.9
             14         0        11     3300.2     2.9
             15         1        11     3300.2     3.8


Simulating `input.scs' on swsrvcomp-18 at 10:31:15 AM, Thur Mar 22, 2018 (process id: 15711).
Current working directory: /simulated/swsrvcomp-54/projects/agnes/members/pcardoso/dfII/simulation/DESIGN/TB_comparators/spectre/schematic/netlist
Command line:
    /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools/bin/spectre  \
        input.scs +escchars +log ../psf/spectre.out -format psfbin -raw  \
        ../psf  \
        -I/cad/lib/pdk/tsmc13bcd_1p6m/shared/models/spectre/tsmc13bcdi.2/multiplelib  \
        +lqtimeout 0 -maxw 5 -maxn 5 +lorder MMSIM

Loading /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/cmi/lib/5.0/libphilips_o_sh.so ...
Loading /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Reading file:  /simulated/swsrvcomp-54/projects/agnes/members/pcardoso/dfII/simulation/DESIGN/TB_comparators/spectre/schematic/netlist/input.scs
Reading file:  /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /cad/lib/pdk/tsmc13bcd_1p6m/shared/models/spectre/tsmc13bcdi.2/multiplelib/active.scs
Reading file:  /cad/lib/pdk/tsmc13bcd_1p6m/shared/models/spectre/tsmc13bcdi.2/multiplelib/cv013lp_tgo_bcd_v1d5p2.scs
Reading file:  /cad/lib/pdk/tsmc13bcd_1p6m/shared/models/spectre/tsmc13bcdi.2/multiplelib/passive.scs
Reading file:  /cad/lib/pdk/tsmc13bcd_1p6m/shared/models/spectre/tsmc13bcdi.2/multiplelib/dialog_rrdl.scs
Reading file:  /cad/lib/pdk/tsmc13bcd_1p6m/shared/models/spectre/tsmc13bcdi.2/multiplelib/Device_without_mismatch_checks.scs
Time for NDB Parsing: CPU = 430.934 ms, elapsed = 994.294 ms.
Time accumulated: CPU = 452.93 ms, elapsed = 994.298 ms.
Peak resident memory used = 36.9 Mbytes.

Reading link:  /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file:  /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading link:  /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file:  /cad/eda/cadence/MMSIM/14.10.664/linux_i/tools.lnx86/spectre/etc/ahdl/constants.vams
Time for Elaboration: CPU = 41.994 ms, elapsed = 42.4201 ms.
Time accumulated: CPU = 495.924 ms, elapsed = 1.03688 s.
Peak resident memory used = 41.2 Mbytes.

Time for EDB Visiting: CPU = 999 us, elapsed = 1.36089 ms.
Time accumulated: CPU = 496.923 ms, elapsed = 1.03838 s.
Peak resident memory used = 41.9 Mbytes.


Warning from spectre during initial setup.
    WARNING (SPECTRE-16684): nch_tgona5_WITHOUT_MISMATCH:Specified model `nch_tgona5' was not found. Assert is ignored.
    WARNING (SPECTRE-16684): pch_tgo5_WITHOUT_MISMATCH:Specified model `pch_tgo5' was not found. Assert is ignored.
    WARNING (SPECTRE-16684): nch_tgo5_WITHOUT_MISMATCH:Specified model `nch_tgo5' was not found. Assert is ignored.
    WARNING (SPECTRE-16684): pnp5_WITHOUT_MISMATCH:Specified model `pnp5' was not found. Assert is ignored.
    WARNING (SPECTRE-16684): pnp2_WITHOUT_MISMATCH:Specified model `pnp2' was not found. Assert is ignored.
        Further occurrences of this warning will be suppressed.
Notice from spectre during topology check.
    Only one connection to the following 4 nodes:
        en_5v
        vdd_1v5
        sine
        step


Global user options:
             reltol = 0.001
            vabstol = 1e-06
            iabstol = 1e-12
               temp = 27
               tnom = 27
             scalem = 1
              scale = 1
               gmin = 1e-12
             rforce = 1
           maxnotes = 5
           maxwarns = 5
             digits = 5
               cols = 80
             pivrel = 0.001
           sensfile = ../psf/sens.output
       dochecklimit = yes
     checklimitdest = both
               save = all
           currents = all
     subcktprobelvl = 2
               tnom = 27
             scalem = 1
              scale = 1

Circuit inventory:
              nodes 20
             iprobe 91    
             assert 20    
              bsim4 21    
          capacitor 1     
              diode 6     
            isource 1     
              relay 1     
            vsource 10    

Analysis and control statement inventory:
         checklimit 2     
                 dc 1     
               info 9     
               tran 1     

Output statements:
             .probe 0     
           .measure 0     
               save 0     


Notice from spectre.
    15 warnings suppressed.

Time for parsing: CPU = 6 ms, elapsed = 8.04996 ms.
Time accumulated: CPU = 503.923 ms, elapsed = 1.04657 s.
Peak resident memory used = 43.2 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~

*************************************
Checklimit Analysis  `dcOpCheckLimit'
*************************************

******************
DC Analysis `dcOp'
******************
Important parameter values:
    reltol = 1e-03
    abstol(V) = 1 uV
    abstol(I) = 1 pA
    temp = 27 C
    tnom = 27 C
    tempeffects = all
    gmindc = 1 pS

Notice from spectre during DC analysis `dcOp'.
    GminDC = 1 pS is large enough to noticeably affect the DC solution.
        dV(Icomp.M12:int_s) = -25.8602 mV
        Use the `gmin_check' option to eliminate or expand this report.
    Bad pivoting is found during DC analysis. Option dc_pivot_check=yes is recommended for possible improvement of convergence.

Convergence achieved in 22 iterations.
Total time required for dc analysis `dcOp': CPU = 4.999 ms, elapsed = 8.04496 ms.
Time accumulated: CPU = 508.922 ms, elapsed = 1.05767 s.
Peak resident memory used = 44.2 Mbytes.

dcOpInfo: writing operating point information to rawfile.

*************************************
Checklimit Analysis  `tranCheckLimit'
*************************************

Warning from spectre during checklimit `tranCheckLimit'.
    WARNING (SPECTRE-16508): Specified severity will override the past specification of the same through another checklimit analysis.


************************************************
Transient Analysis `tran': time = (0 s -> 15 ms)
************************************************

Notice from spectre during IC analysis, during transient analysis `tran'.
    GminDC = 1 pS is large enough to noticeably affect the DC solution.
        dV(Icomp.M13:int_s) = -25.9185 mV
        Use the `gmin_check' option to eliminate or expand this report.
    Bad pivoting is found during DC analysis. Option dc_pivot_check=yes is recommended for possible improvement of convergence.

DC simulation time: CPU = 1.999 ms, elapsed = 1.80221 ms.
Important parameter values:
    start = 0 s
    outputstart = 0 s
    stop = 15 ms
    step = 15 us
    maxstep = 300 us
    ic = all
    useprevic = no
    skipdc = no
    reltol = 1e-03
    abstol(V) = 1 uV
    abstol(I) = 1 pA
    temp = 27 C
    tnom = 27 C
    tempeffects = all
    errpreset = moderate
    method = traponly
    lteratio = 3.5
    relref = sigglobal
    cmin = 0 F
    gmin = 1 pS


Output and IC/nodeset summary:
                 save   394     (current)
                 save   136     (voltage)

    tran: time = 433.3 us    (2.89 %), step = 83.33 us     (556 m%)

Error found by spectre at time = 521.986 us during transient analysis `tran'.
    ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified.  Last acceptable solution computed at 500.051 us.

The values for those nodes that did not converge on the last Newton iteration are given below.  The manner in which the convergence criteria were not satisfied is also given.
            Failed test: | Value | > RelTol*Ref + AbsTol

 Top 10 Solution too large Convergence failure:
    I(Icomp.M2:4) = 307.984 uA, previously -32.3203 nA.
        update too large:  | 284.482 uA | > 310.877 nA + 1 pA
    I(Icomp.M2:3) = -310.567 uA, previously 322.348 nA.
        update too large:  | -284.386 uA | > 313.459 nA + 1 pA
    I(Icomp.M1:3) = 919.296 uA, previously -5.08823 nA.
        update too large:  | -238.885 uA | > 922.188 nA + 1 pA
    I(Icomp.M5:3) = -15.0765 uA, previously 255.639 nA.
        update too large:  | 4.16553 uA | > 17.9687 nA + 1 pA
    I(Icomp.Npdleg1:1) = -1.44554 mA, previously 1.18652 nA.
        update too large:  | 267.578 uA | > 1.44843 uA + 1 pA
    I(Icomp.Npdleg1:2) = 1.9605 mA, previously -1.54427 nA.
        update too large:  | -360.998 uA | > 1.96339 uA + 1 pA
    I(Icomp.Npdleg1:5) = -514.963 uA, previously -849.292 fA.
        update too large:  | 93.4199 uA | > 517.855 nA + 1 pA
    I(Icomp.M5:4) = -9.77689 mA, previously 3.1136 nA.
        update too large:  | -1.37557 mA | > 9.77979 uA + 1 pA
    I(Icomp.M1:1) = 9.78944 mA, previously -29.6206 nA.
        update too large:  | 1.37148 mA | > 9.79233 uA + 1 pA
    I(Icomp:7) = 9.79036 mA, previously -873.229 nA.
        update too large:  | 1.37137 mA | > 9.79325 uA + 1 pA
 Top 10 Residue too large Convergence failure:
    V(Icomp.M3:int_d) = -19.2525 V, previously 944.113 mV.
        residue too large: | 83.0207 A | > 83.0207 mA + 1 pA
    V(Icomp.M4:int_d) = 12.8343 V, previously 39.8285 mV.
        residue too large: | -31.7483 A | > 31.7483 mA + 1 pA
    V(Icomp.Npdleg1.M0:int_d) = -19.1371 V, previously 944.113 mV.
        residue too large: | 18.4233 A | > 18.4233 mA + 1 pA
    V(Icomp.Npdsimfsto.M0:int_d) = 12.8343 V, previously 39.8286 mV.
        residue too large: | -5.29138 A | > 5.29138 mA + 1 pA
    V(Icomp.Ppusimovin:int_s) = 4.04351 V, previously 2.36301 V.
        residue too large: | 682.863 mA | > 682.863 uA + 1 pA
    V(Icomp.M13:int_s) = 4.15755 V, previously 2.36301 V.
        residue too large: | 614.031 mA | > 614.031 uA + 1 pA
    V(Icomp.M12:int_s) = 4.15755 V, previously 2.36301 V.
        residue too large: | 614.031 mA | > 614.031 uA + 1 pA
    V(Icomp.M2:int_s) = 14.4799 V, previously 1.5591 V.
        residue too large: | -237.545 A | > 237.545 mA + 1 pA
    V(Icomp.M1:int_d) = -5.27101 V, previously 944.113 mV.
        residue too large: | 109.377 A | > 109.377 mA + 1 pA
    V(Icomp.Npdleg1.M0:int_s) = 834.857 uV, previously 1.37687 pV.
        residue too large: | -4.89987 mA | > 4.89987 uA + 1 pA


The following set of suggestions might help you avoid convergence difficulties.  

 1. Evaluate and resolve any notice, warning, or error messages.
 2. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
 3. Small floating resistors connected to high impedance nodes can cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
 4. Ensure that a complete set of parasitic capacitors is used on nonlinear devices to avoid jumps in the solution waveforms. On MOS models, specify nonzero source and drain areas.
 5. Perform sanity check on the parameter values by using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings.  Print the minimum and maximum parameter value by using `info' analysis.  Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.

 6. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.

 7.  Enable diagnostic messages by setting option `diagnose=detailed'.
 8. Use the `cmin' parameter to install a small capacitor from every node in the circuit to ground.  This usually eliminates any jump in the solution.
 9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
10. Try to simplify the nonlinear component models to avoid regions that might contribute to convergence problems in the model.

Analysis `tran' was terminated prematurely due to an error.
finalTimeOP: writing operating point information to rawfile.

Notice from spectre during DC analysis, during info `finalTimeOP'.
    GminDC = 1 pS is large enough to noticeably affect the DC solution.
        dV(Icomp.M12:int_s) = -25.8604 mV
        Use the `gmin_check' option to eliminate or expand this report.

DC simulation time: CPU = 2 ms, elapsed = 2.32482 ms.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.
asserts: writing assert to rawfile.

Aggregate audit (10:31:17 AM, Thur Mar 22, 2018):
Time used: CPU = 1.07 s, elapsed = 1.67 s, util. = 64.1%.
Time spent in licensing: elapsed = 491 ms, percentage of total = 29.5%.
Peak memory used = 46.1 Mbytes.
Simulation started at: 10:31:15 AM, Thur Mar 22, 2018, ended at: 10:31:17 AM, Thur Mar 22, 2018, with elapsed time (wall clock): 1.67 s.
spectre completes with 1 error, 6 warnings, and 7 notices.

-WRAPPER- PWD: /simulated/swsrvcomp-54/projects/agnes/members/pcardoso/dfII/simulation/DESIGN/TB_comparators/spectre/schematic/netlist
-WRAPPER- /simulated/swsrvcomp-54 has 10124GB of free space and is 1% full.
-WRAPPER- Recognized requirements: NSLOTS: not_def MT: not_set APS: not_set  => MMTOKEN 1
-WRAPPER- Created Pholder File LclSpectre_Pholder_pcardoso_swsrvcomp-18_15669
-WRAPPER- Spectre run locally is precompiling C-Code with a single thread. (decreased performace for bigger VerilogA code)
-WRAPPER- Invoking: spectre input.scs +escchars +log ../psf/spectre.out -format psfbin -raw ../psf -I/cad/lib/pdk/tsmc13bcd_1p6m/shared/models/spectre/tsmc13bcdi.2/multiplelib +lqtimeout 0 -maxw 5 -maxn 5  +lorder MMSIM
-WRAPPER- Setting CDS_AHDL_REUSE_LIB=NO ...
-WRAPPER- Launching spectre exclusively on cpu 1 (swsrvcomp-18)...
-WRAPPER DEBUG- Pid of spawned SPECTRE: 15698
-MONITOR- monitor(pid = 15712) started, spectre binary = 15711, top process = 15666
-WRAPPER- WARNING: Spectre exited with status 1
-WRAPPER- Removed Pholder File LclSpectre_Pholder_pcardoso_swsrvcomp-18_15669
-WRAPPER- Results folder size is [KB] 1636	../psf

-WRAPPER- Log in: /cad/var/log/simulation_logs/201803_2/spectre_pcardoso_swsrvcomp-18_15669_Thu_Mar_22_10:31:15_2018.log.gz

    Fullscreen TBcomparator_netlist.txt Download 
    // Generated for: spectre
// Generated on: Mar 22 10:31:14 2018
// Design library name: DESIGN
// Design cell name: TB_comparators
// Design view name: schematic
simulator lang=spectre
global 0
parameters en_sine=0 en_step=0 en_pulse=1 frequency=1k Vos=-173u Cload=1p \
    en_1v5=1 en_5v=1 Idd=250n PSRR_en=0 vdd_1v5=1.5 vdd_5v0=3.8 vref=0.75
include "active.scs" section=tt
include "passive.scs" section=pass_nom
include "Device_without_mismatch_checks.scs"

// Library name: disc13ip
// Cell name: nmos5v_iso
// View name: schematic
subckt nmos5v_iso B D DN G S SUB
parameters area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=2u l=600n fingers=1 as=8.2e-13 ad=8.2e-13 ps=4.82u pd=4.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.105 nrs=0.105 \
        mismatchflag=1 sigma=1
    D1 (SUB DN) nblpsubhvpw_dio_iso area=area_nblpsubhvpw_dio_iso \
        pj=pj_nblpsubhvpw_dio_iso m=multiGL
    D0 (B DN) pwnblhvnw_dio_iso area=area_pwnblhvnw_dio_iso \
        pj=pj_pwnblhvnw_dio_iso m=multiGL
    M0 (D G S B) nch_tgo5_mac w=w l=l nf=fingers as=as ad=ad ps=ps pd=pd \
        sa=sa sb=sb sd=sd nrd=nrd nrs=nrs multi=multiGL \
        mismatchflag=mismatchflag sigma=sigma
ends nmos5v_iso
// End of subcircuit definition.

// Library name: d50r3s
// Cell name: v5inv_1x
// View name: schematic
subckt v5inv_1x IN0 Y inh_dig_vdd inh_dig_vss inh_nbulk
    M1 (Y IN0 inh_dig_vdd inh_dig_vdd) pch_tgo5_mac w=1.13u l=600n nf=1 \
        as=4.068e-13 ad=4.068e-13 ps=2.98u pd=2.98u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.185841 nrs=0.185841 multi=1 mismatchflag=1 \
        sigma=1
    M0 (Y IN0 inh_dig_vss inh_nbulk) nch_tgo5_mac w=800n l=600n nf=1 \
        as=2.88e-13 ad=2.88e-13 ps=2.32u pd=2.32u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.2625 nrs=0.2625 multi=1 mismatchflag=1 sigma=1
ends v5inv_1x
// End of subcircuit definition.

// Library name: DESIGN
// Cell name: comparator
// View name: schematic
subckt comparator en_1v5 ibias in_n in_p out vdd vss
    M6 (out out_1st vss vss) nch_tgo5_mac w=1.92u l=600n nf=1 as=7.872e-13 \
        ad=7.872e-13 ps=4.66u pd=4.66u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.109375 nrs=0.109375 multi=2 mismatchflag=1 sigma=1
    M3 (loads loads vss vss) nch_tgo5_mac w=3u l=10u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=2 mismatchflag=1 sigma=1
    M4 (out_1st loads vss vss) nch_tgo5_mac w=3u l=10u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=2 mismatchflag=1 sigma=1
    M14 (pmirror ibias vss vss) nch_tgo5_mac w=10u l=10u nf=1 as=4.1e-12 \
        ad=4.1e-12 ps=20.82u pd=20.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.021 nrs=0.021 multi=1 mismatchflag=1 sigma=1
    M0 (ibias ibias vss vss) nch_tgo5_mac w=10u l=10u nf=1 as=4.1e-12 \
        ad=4.1e-12 ps=20.82u pd=20.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.021 nrs=0.021 multi=1 mismatchflag=1 sigma=1
    Npdsimfsto (vss out_1st vdd_5v0 en_n_5v vss vss) nmos5v_iso \
        area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \
        sigma=1
    Npdleg1 (vss loads vdd_5v0 en_n_5v vss vss) nmos5v_iso \
        area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \
        sigma=1
    N0 (vss ibias vdd_5v0 en_n_5v vss vss) nmos5v_iso \
        area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \
        sigma=1
    Ppusimovin (pmirror en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 \
        as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    P_pup_tail (tail en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 \
        as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    M13 (in_n en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 as=4.1e-13 \
        ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    M12 (in_p en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 as=4.1e-13 \
        ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    M7 (out pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=16 mismatchflag=1 sigma=1
    M5 (tail pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=4 mismatchflag=1 sigma=1
    M9 (pmirror pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 \
        as=1.23e-12 ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.07 nrs=0.07 multi=4 mismatchflag=1 sigma=1
    M2 (out_1st in_p tail tail) pch_tgo5_mac w=20u l=2u nf=2 as=8.2e-12 \
        ad=4.2e-12 ps=41.64u pd=20.84u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.0105 nrs=0.0105 multi=2 mismatchflag=1 sigma=1
    M1 (loads in_n tail tail) pch_tgo5_mac w=20u l=2u nf=2 as=8.2e-12 \
        ad=4.2e-12 ps=41.64u pd=20.84u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.0105 nrs=0.0105 multi=2 mismatchflag=1 sigma=1
    I7 (en_n_5v en vdd vss vss) v5inv_1x
    I5 (en_1v5 en_n_5v vdd vss vss) v5inv_1x
ends comparator
// End of subcircuit definition.

// Library name: DESIGN
// Cell name: TB_comparators
// View name: schematic
W7 (pulse stimuli 0 net06) relay vt1=3 vt2=0 ropen=1T rclosed=100n
V10 (net06 0) vsource dc=en_pulse*1.5 type=dc
V3 (vref 0) vsource dc=vref type=dc
V11 (en_5v 0) vsource dc=en_5v*vdd_5v0 type=dc
V13 (en_1v5 0) vsource dc=en_1v5*vdd_5v0 type=dc
V1 (vss 0) vsource dc=0 mag=PSRR_en type=dc
V0 (vdd_1v5 0) vsource dc=vdd_1v5 type=dc
V14 (vdd_5v0 0) vsource dc=vdd_5v0 mag=PSRR_en type=dc
V4 (sine 0) vsource dc=vref type=sine ampl=100.0m sinephase=0 \
        freq=frequency
C0 (out vss) capacitor c=Cload
I12 (vdd_5v0 net11) isource dc=Idd type=dc
Icomp (en_1v5 net11 stimuli vref out vdd_5v0 vss) comparator
V2 (pulse 0) vsource dc=vref type=pulse val0=0 val1=vdd_1v5 period=2m \
        delay=500u rise=50n fall=50n width=1.5ms
V6 (step 0) vsource dc=vref type=pwl wave=[ 0 0 100u 0 ]
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    dochecklimit=yes checklimitdest=both 
dcOpCheckLimit checklimit checkallasserts=yes severity=none
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
tranCheckLimit checklimit checkallasserts=yes severity=none
tran tran stop=15m errpreset=moderate write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
asserts info what=assert where=rawfile
saveOptions options save=all currents=all subcktprobelvl=2

    No convergence case (Pulse voltage source only )

    With the 3 relays, converges but the output waveform (stimuli net) shows a funny shape.

    Netlist for this case,

    Fullscreen TBcomparator_netlist2.txt Download 
    // Generated for: spectre
// Generated on: Mar 22 10:54:46 2018
// Design library name: DESIGN
// Design cell name: TB_comparators
// Design view name: schematic
simulator lang=spectre
global 0
parameters en_sine=0 en_step=0 en_pulse=1 frequency=1k Vos=-173u Cload=1p \
    en_1v5=1 en_5v=1 Idd=250n PSRR_en=0 vdd_1v5=1.5 vdd_5v0=3.8 vref=0.75
include "active.scs" section=tt
include "passive.scs" section=pass_nom
include "Device_without_mismatch_checks.scs"

// Library name: disc13ip
// Cell name: nmos5v_iso
// View name: schematic
subckt nmos5v_iso B D DN G S SUB
parameters area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=2u l=600n fingers=1 as=8.2e-13 ad=8.2e-13 ps=4.82u pd=4.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.105 nrs=0.105 \
        mismatchflag=1 sigma=1
    D1 (SUB DN) nblpsubhvpw_dio_iso area=area_nblpsubhvpw_dio_iso \
        pj=pj_nblpsubhvpw_dio_iso m=multiGL
    D0 (B DN) pwnblhvnw_dio_iso area=area_pwnblhvnw_dio_iso \
        pj=pj_pwnblhvnw_dio_iso m=multiGL
    M0 (D G S B) nch_tgo5_mac w=w l=l nf=fingers as=as ad=ad ps=ps pd=pd \
        sa=sa sb=sb sd=sd nrd=nrd nrs=nrs multi=multiGL \
        mismatchflag=mismatchflag sigma=sigma
ends nmos5v_iso
// End of subcircuit definition.

// Library name: d50r3s
// Cell name: v5inv_1x
// View name: schematic
subckt v5inv_1x IN0 Y inh_dig_vdd inh_dig_vss inh_nbulk
    M1 (Y IN0 inh_dig_vdd inh_dig_vdd) pch_tgo5_mac w=1.13u l=600n nf=1 \
        as=4.068e-13 ad=4.068e-13 ps=2.98u pd=2.98u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.185841 nrs=0.185841 multi=1 mismatchflag=1 \
        sigma=1
    M0 (Y IN0 inh_dig_vss inh_nbulk) nch_tgo5_mac w=800n l=600n nf=1 \
        as=2.88e-13 ad=2.88e-13 ps=2.32u pd=2.32u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.2625 nrs=0.2625 multi=1 mismatchflag=1 sigma=1
ends v5inv_1x
// End of subcircuit definition.

// Library name: DESIGN
// Cell name: comparator
// View name: schematic
subckt comparator en_1v5 ibias in_n in_p out vdd vss
    M6 (out out_1st vss vss) nch_tgo5_mac w=1.92u l=600n nf=1 as=7.872e-13 \
        ad=7.872e-13 ps=4.66u pd=4.66u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.109375 nrs=0.109375 multi=2 mismatchflag=1 sigma=1
    M3 (loads loads vss vss) nch_tgo5_mac w=3u l=10u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=2 mismatchflag=1 sigma=1
    M4 (out_1st loads vss vss) nch_tgo5_mac w=3u l=10u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=2 mismatchflag=1 sigma=1
    M14 (pmirror ibias vss vss) nch_tgo5_mac w=10u l=10u nf=1 as=4.1e-12 \
        ad=4.1e-12 ps=20.82u pd=20.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.021 nrs=0.021 multi=1 mismatchflag=1 sigma=1
    M0 (ibias ibias vss vss) nch_tgo5_mac w=10u l=10u nf=1 as=4.1e-12 \
        ad=4.1e-12 ps=20.82u pd=20.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.021 nrs=0.021 multi=1 mismatchflag=1 sigma=1
    Npdsimfsto (vss out_1st vdd_5v0 en_n_5v vss vss) nmos5v_iso \
        area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \
        sigma=1
    Npdleg1 (vss loads vdd_5v0 en_n_5v vss vss) nmos5v_iso \
        area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \
        sigma=1
    N0 (vss ibias vdd_5v0 en_n_5v vss vss) nmos5v_iso \
        area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \
        sigma=1
    Ppusimovin (pmirror en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 \
        as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    P_pup_tail (tail en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 \
        as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    M13 (in_n en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 as=4.1e-13 \
        ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    M12 (in_p en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 as=4.1e-13 \
        ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    M7 (out pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=16 mismatchflag=1 sigma=1
    M5 (tail pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=4 mismatchflag=1 sigma=1
    M9 (pmirror pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 \
        as=1.23e-12 ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.07 nrs=0.07 multi=4 mismatchflag=1 sigma=1
    M2 (out_1st in_p tail tail) pch_tgo5_mac w=20u l=2u nf=2 as=8.2e-12 \
        ad=4.2e-12 ps=41.64u pd=20.84u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.0105 nrs=0.0105 multi=2 mismatchflag=1 sigma=1
    M1 (loads in_n tail tail) pch_tgo5_mac w=20u l=2u nf=2 as=8.2e-12 \
        ad=4.2e-12 ps=41.64u pd=20.84u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.0105 nrs=0.0105 multi=2 mismatchflag=1 sigma=1
    I7 (en_n_5v en vdd vss vss) v5inv_1x
    I5 (en_1v5 en_n_5v vdd vss vss) v5inv_1x
ends comparator
// End of subcircuit definition.

// Library name: DESIGN
// Cell name: TB_comparators
// View name: schematic
W0 (sine stimuli 0 net05) relay vt1=3 vt2=0 ropen=1T rclosed=1n
W7 (pulse stimuli 0 net06) relay vt1=3 vt2=0 ropen=1T rclosed=1n
W8 (step stimuli 0 net07) relay vt1=3 vt2=0 ropen=1T rclosed=1n
V5 (net05 0) vsource dc=en_sine*1.5 type=dc
V10 (net06 0) vsource dc=en_pulse*1.5 type=dc
V12 (net07 0) vsource dc=en_step*1.5 type=dc
V3 (vref 0) vsource dc=vref type=dc
V11 (en_5v 0) vsource dc=en_5v*vdd_5v0 type=dc
V13 (en_1v5 0) vsource dc=en_1v5*vdd_5v0 type=dc
V1 (vss 0) vsource dc=0 mag=PSRR_en type=dc
V0 (vdd_1v5 0) vsource dc=vdd_1v5 type=dc
V14 (vdd_5v0 0) vsource dc=vdd_5v0 mag=PSRR_en type=dc
V4 (sine 0) vsource dc=vref type=sine ampl=100.0m sinephase=0 \
        freq=frequency
C0 (out vss) capacitor c=Cload
I12 (vdd_5v0 net11) isource dc=Idd type=dc
Icomp (en_1v5 net11 stimuli vref out vdd_5v0 vss) comparator
V2 (pulse 0) vsource dc=vref type=pulse val0=0 val1=vdd_1v5 period=2m \
        delay=500u rise=50n fall=50n width=1.5ms
V6 (step 0) vsource dc=vref type=pwl wave=[ 0 0 100u 0 ]
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    dochecklimit=yes checklimitdest=both 
dcOpCheckLimit checklimit checkallasserts=yes severity=none
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
tranCheckLimit checklimit checkallasserts=yes severity=none
tran tran stop=15m errpreset=moderate write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
asserts info what=assert where=rawfile
saveOptions options save=all currents=all subcktprobelvl=2

    I am sorry for the long e-mail.

    Best regards,

    Pedro

  • Andrew Beckett
    in reply to netbug

    Hi Pedro,

    There are a few things wrong:

    1. Assuming your en_sine, en_pulse, en_step are supposed to be "active high" (so 0 is disabled, 1 is enabled) the switch (relay) components have the control connections upside down. This is because you rotated the component by 180 degrees. That means the control signal is either 0 or -1.5V whereas I think you want them to be 0 or 1.5. You can see this because the 3rd and 4th connections appear to be the wrong way around with 0 (ground) being the third connection.
    2. You have the vt1 values as 3V which means that the relay wouldn't have been fully switched even if they were connected up the right way around. I think you should have vt1=0 and vt2=1.5 on the switch/relay components
    3. I wouldn't use such a small on resistance value - that's not good for convergence. Don't use anything lower than 1mOhm
    4. You should add a resistor (1Tohm is fine) from stimuli to ground to ensure there's a path to ground. Normally this is done for active devices, but this helps with convergence when the switch is off.

    Here's what I changed in the netlist:

    W0 (sine stimuli net05 0) relay vt1=0 vt2=1.5 ropen=1T rclosed=1m
    W7 (pulse stimuli net06 0) relay vt1=0 vt2=1.5 ropen=1T rclosed=1m
    W8 (step stimuli net07 0) relay vt1=0 vt2=1.5 ropen=1T rclosed=1m
    Rl (stimuli 0) resistor r=1T

    With that, it works well. What you were seeing was that everything was turned on.

    Regards,

    Andrew.

  • netbug
    in reply to Andrew Beckett

    Hi Andrew,

    Thanks for the comments. I had rotated the relays indeed.

    Now I have everything correctly wired, but the net stimuli has all the signals added together (everything on)

    To debug this, I removed the label stimuli from all the three relays and replaced them with sine_o, pulse_o and step_o. Probing these nets show that, despite the relay being open, the waveform passes to the output of the switch. Shouldn't the 1Tohm resistor kill the signal ?

    Is there a way to kill a voltage source when I don't need it. I had enable variables inside each source, forcing the voltage to be 0 when I wanted it disabled, but I am not sure that this is the right approach.

    In the screenshots below, you can see that I've removed the label stimuli, and even that way, the signal shows on the "output" of the switch.

    In the figure below, I was expecting to see the sine output only and not the others since the switch is open.

    Fullscreen netlist_1.txt Download 
    // Generated for: spectre
// Generated on: Mar 22 16:26:55 2018
// Design library name: DESIGN
// Design cell name: TB_comparators
// Design view name: schematic
simulator lang=spectre
global 0
parameters en_sine=1 en_step=0 en_pulse=0 frequency=1k Vos=-173u Cload=1p \
    en_1v5=1 en_5v=1 Idd=250n PSRR_en=0 vdd_1v5=1.5 vdd_5v0=3.8 vref=0.75
include "active.scs" section=tt
include "passive.scs" section=pass_nom
include "Device_without_mismatch_checks.scs"

// Library name: disc13ip
// Cell name: nmos5v_iso
// View name: schematic
subckt nmos5v_iso B D DN G S SUB
parameters area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=2u l=600n fingers=1 as=8.2e-13 ad=8.2e-13 ps=4.82u pd=4.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.105 nrs=0.105 \
        mismatchflag=1 sigma=1
    D1 (SUB DN) nblpsubhvpw_dio_iso area=area_nblpsubhvpw_dio_iso \
        pj=pj_nblpsubhvpw_dio_iso m=multiGL
    D0 (B DN) pwnblhvnw_dio_iso area=area_pwnblhvnw_dio_iso \
        pj=pj_pwnblhvnw_dio_iso m=multiGL
    M0 (D G S B) nch_tgo5_mac w=w l=l nf=fingers as=as ad=ad ps=ps pd=pd \
        sa=sa sb=sb sd=sd nrd=nrd nrs=nrs multi=multiGL \
        mismatchflag=mismatchflag sigma=sigma
ends nmos5v_iso
// End of subcircuit definition.

// Library name: d50r3s
// Cell name: v5inv_1x
// View name: schematic
subckt v5inv_1x IN0 Y inh_dig_vdd inh_dig_vss inh_nbulk
    M1 (Y IN0 inh_dig_vdd inh_dig_vdd) pch_tgo5_mac w=1.13u l=600n nf=1 \
        as=4.068e-13 ad=4.068e-13 ps=2.98u pd=2.98u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.185841 nrs=0.185841 multi=1 mismatchflag=1 \
        sigma=1
    M0 (Y IN0 inh_dig_vss inh_nbulk) nch_tgo5_mac w=800n l=600n nf=1 \
        as=2.88e-13 ad=2.88e-13 ps=2.32u pd=2.32u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.2625 nrs=0.2625 multi=1 mismatchflag=1 sigma=1
ends v5inv_1x
// End of subcircuit definition.

// Library name: DESIGN
// Cell name: comparator
// View name: schematic
subckt comparator en_1v5 ibias in_n in_p out vdd vss
    M6 (out out_1st vss vss) nch_tgo5_mac w=1.92u l=600n nf=1 as=7.872e-13 \
        ad=7.872e-13 ps=4.66u pd=4.66u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.109375 nrs=0.109375 multi=2 mismatchflag=1 sigma=1
    M3 (loads loads vss vss) nch_tgo5_mac w=3u l=10u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=2 mismatchflag=1 sigma=1
    M4 (out_1st loads vss vss) nch_tgo5_mac w=3u l=10u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=2 mismatchflag=1 sigma=1
    M14 (pmirror ibias vss vss) nch_tgo5_mac w=10u l=10u nf=1 as=4.1e-12 \
        ad=4.1e-12 ps=20.82u pd=20.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.021 nrs=0.021 multi=1 mismatchflag=1 sigma=1
    M0 (ibias ibias vss vss) nch_tgo5_mac w=10u l=10u nf=1 as=4.1e-12 \
        ad=4.1e-12 ps=20.82u pd=20.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.021 nrs=0.021 multi=1 mismatchflag=1 sigma=1
    Npdsimfsto (vss out_1st vdd_5v0 en_n_5v vss vss) nmos5v_iso \
        area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \
        sigma=1
    Npdleg1 (vss loads vdd_5v0 en_n_5v vss vss) nmos5v_iso \
        area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \
        sigma=1
    N0 (vss ibias vdd_5v0 en_n_5v vss vss) nmos5v_iso \
        area_nblpsubhvpw_dio_iso=1.48225e-10 \
        pj_nblpsubhvpw_dio_iso=4.87e-05 multiGL=(1) \
        area_pwnblhvnw_dio_iso=1.2775e-11 pj_pwnblhvnw_dio_iso=1.43e-05 \
        w=1u l=1u fingers=1 as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u \
        sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 nrd=0.21 nrs=0.21 mismatchflag=1 \
        sigma=1
    Ppusimovin (pmirror en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 \
        as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    P_pup_tail (tail en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 \
        as=4.1e-13 ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    M13 (in_n en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 as=4.1e-13 \
        ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    M12 (in_p en vdd_5v0 vdd_5v0) pch_tgo5_mac w=1u l=1u nf=1 as=4.1e-13 \
        ad=4.1e-13 ps=2.82u pd=2.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.21 nrs=0.21 multi=1 mismatchflag=1 sigma=1
    M7 (out pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=16 mismatchflag=1 sigma=1
    M5 (tail pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 as=1.23e-12 \
        ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.07 nrs=0.07 multi=4 mismatchflag=1 sigma=1
    M9 (pmirror pmirror vdd vdd) pch_tgo5_mac w=3u l=12.0u nf=1 \
        as=1.23e-12 ad=1.23e-12 ps=6.82u pd=6.82u sa=4.1e-07 sb=4.1e-07 \
        sd=4.2e-07 nrd=0.07 nrs=0.07 multi=4 mismatchflag=1 sigma=1
    M2 (out_1st in_p tail tail) pch_tgo5_mac w=20u l=2u nf=2 as=8.2e-12 \
        ad=4.2e-12 ps=41.64u pd=20.84u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.0105 nrs=0.0105 multi=2 mismatchflag=1 sigma=1
    M1 (loads in_n tail tail) pch_tgo5_mac w=20u l=2u nf=2 as=8.2e-12 \
        ad=4.2e-12 ps=41.64u pd=20.84u sa=4.1e-07 sb=4.1e-07 sd=4.2e-07 \
        nrd=0.0105 nrs=0.0105 multi=2 mismatchflag=1 sigma=1
    I7 (en_n_5v en vdd vss vss) v5inv_1x
    I5 (en_1v5 en_n_5v vdd vss vss) v5inv_1x
ends comparator
// End of subcircuit definition.

// Library name: DESIGN
// Cell name: TB_comparators
// View name: schematic
W2 (step_o step net07 0) relay vt1=1.5 vt2=0 ropen=1T rclosed=1m
W1 (pulse_o pulse net06 0) relay vt1=1.5 vt2=0 ropen=1T rclosed=1m
W0 (sine_o sine net05 0) relay vt1=1.5 vt2=0 ropen=1T rclosed=1m
V5 (net05 0) vsource dc=en_sine*1.5 type=dc
V10 (net06 0) vsource dc=en_pulse*1.5 type=dc
V12 (net07 0) vsource dc=en_step*1.5 type=dc
V3 (vref 0) vsource dc=vref type=dc
V11 (en_5v 0) vsource dc=en_5v*vdd_5v0 type=dc
V13 (en_1v5 0) vsource dc=en_1v5*vdd_5v0 type=dc
V1 (vss 0) vsource dc=0 mag=PSRR_en type=dc
V0 (vdd_1v5 0) vsource dc=vdd_1v5 type=dc
V14 (vdd_5v0 0) vsource dc=vdd_5v0 mag=PSRR_en type=dc
V4 (sine 0) vsource dc=vref type=sine ampl=100.0m sinephase=0 \
        freq=frequency
C0 (out vss) capacitor c=Cload
I12 (vdd_5v0 net11) isource dc=Idd type=dc
R0 (stimuli 0) resistor r=1T
Icomp (en_1v5 net11 stimuli vref out vdd_5v0 vss) comparator
V2 (pulse 0) vsource dc=vref type=pulse val0=0 val1=vdd_1v5 period=2m \
        delay=500u rise=50n fall=50n width=1.5ms
V6 (step 0) vsource dc=vref type=pwl wave=[ 0 0 1m 0 1.01m (vdd_1v5) 5m \
        (vdd_1v5) 5.01m 0 ]
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    dochecklimit=yes checklimitdest=both 
dcOpCheckLimit checklimit checkallasserts=yes severity=none
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
tranCheckLimit checklimit checkallasserts=yes severity=none
tran tran stop=15m errpreset=moderate write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
asserts info what=assert where=rawfile
saveOptions options save=all currents=all subcktprobelvl=2

    Thanks for your time.

    Best regards,

    Pedro

  • Andrew Beckett
    in reply to netbug

    Pedro,

    You haven't swapped vt1 and vt2 (the Open and Closed voltage) - you have the Open Voltage (vt1) at 1.5 which means that a high value (1) for your en_sine, en_pulse and en_step parameters will mean that those sources are disconnected (proviso below - they are weakly connected) whereas when they are at 0, they are strongly connected.

    So either swap the two values or your enables are active low.

    The proviso is that when you disconnect each source to step_o, sine_o, pulse_o, there is no load (they are open circuit). So you either have the source connected to the node via a 1m resistor or a 1Tohm resistor - in both cases the voltage at the end of an open circuit is going to be the same as the input source. If you added (say) a 1k resistor to ground on the sine_o, pulse_o and step_o nodes, then you'd see the signals changing correctly depending on the state of the relay.

    Regards,

    Andrew.

  • netbug
    in reply to Andrew Beckett

    Hi Andrew,

    I swapped vt1 and vt2, as you said, re-named en_pulse, en_sine, en_step back to "stimuli" and hanged a 10k resistor from "stimuli" to ground. 

    And .. it is working now :-)

    Thank you very much for your help.

    Best regards,

    Pedro

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