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Crude auto-layout SKILL to Virtuoso

goofycat

Hi,

In virtuoso, one can add Verilog type Cellview, and it can get compiled. For the least, this result in RTL netlist.

For millions of registers, one definitely needs Encounter for layout generation. However, some small functional chips might have just few hundreds of registers like for simple CPLD. In this case, there is not such strict timing constraint and the more liberty to take in placing the registers.

If one uses simple tools like Yosys (several MBs) to create RTL, then writing some simple computational geometry algorithm to do the layout (for small number), and convert the result to SKILL commands which do the placement, run the SKILL in Virtuoso CIW, we might get a less-than-optimal automatically generated layout. We can then carefully check Diva/Dracula/LVS rules, and get the result to pass verification.

If we try this approach, is there any particular pitfalls to be wary of?

customer

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  • Marc Heise

    Hi,

    if timing isn't a concern and you have low numbers of cells ( several thousands should be doable ) to place   you could use our VCP ( Virtuoso Custom Placer ) , it's working based on a schematic input, does row based placement, can insert fillers and will optimize for routing length. It's probably easier to import your RTL  into a Virtuoso schematic than to write your own placer.

    Kind regards,

    Marc

Reply
  • Marc Heise

    Hi,

    if timing isn't a concern and you have low numbers of cells ( several thousands should be doable ) to place   you could use our VCP ( Virtuoso Custom Placer ) , it's working based on a schematic input, does row based placement, can insert fillers and will optimize for routing length. It's probably easier to import your RTL  into a Virtuoso schematic than to write your own placer.

    Kind regards,

    Marc

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