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How to use a component (VerilogA) within a .scs model file to drive output signals

MT13

Hi,

I have a .scs model file for a digital block. The digital block has some multi-bit (bus) outputs. At the end of the .scs file, there are a bunch of statements to drive the outputs of the blocks:

v1 (demux\<0\> gnd) vsource type=dc dc=0

and this is repeated for each bit of the multi-bit signal.

This model file is added: ADE -> setup -> simulation files --> (added in the definition files category), and the testbench runs successfully.

Instead of driving each bit along, I would like to drive the whole bus (ideally with an analog value that gets translated during simulation). I have a VerilogA analog to digital component (tested and works) that I would like to use to drive that bus, the syntax that I used is:

AD1 (demux\<3\:0\>) adc_4b one=vdd zero=0 num=demux_val

At first the simulation failed complaining that adc_4b is not defined (although the library containing it is added to the library path in the library manager). I added the veriloga (.va) file that defines the component, once to setup--> simulation files --> definition files, and once to setup--> model files, and in both times the simulation fails because of a whole bunch of errors that seem to be VerilogA parsing errors, for example:

ERROR : (SFE - 874) "path" : unexpected quote character "`". Cannot run the simulation because of syntax error.

and so on.

veriloga is added to the switch view and stop view fields in setup --> environment

I am using IC6.1.7-64b.500.16

Thank you in advance

Parents
  • Andrew Beckett

    The netlister can't automatically include it because it has no idea you're referencing it - normally if the netlister netlists a schematic hierarchy which switches into a veriloga view, it will automatically add the ahdl_include statement into the netlist.

    Directly referencing the VerilogA in the definition files or model files won't work because it is not a spectre syntax file - and so you cannot directly include the file via an "include" statement.

    So, in your .scs file, add a line:

    ahdl_include "/path/to/veriloga/veriloga.va"

    and then spectre will be able to see the definition.

    Regards,

    Andrew.

Reply
  • Andrew Beckett

    The netlister can't automatically include it because it has no idea you're referencing it - normally if the netlister netlists a schematic hierarchy which switches into a veriloga view, it will automatically add the ahdl_include statement into the netlist.

    Directly referencing the VerilogA in the definition files or model files won't work because it is not a spectre syntax file - and so you cannot directly include the file via an "include" statement.

    So, in your .scs file, add a line:

    ahdl_include "/path/to/veriloga/veriloga.va"

    and then spectre will be able to see the definition.

    Regards,

    Andrew.

Children
  • MT13
    in reply to Andrew Beckett

    Hi Andew,

    Thank you for the answer, it works.

    I hope I am not violating forum guidelines by asking a follow up question, but now the simulation is failing because of an CMI-2116 error: I0.AD1: Too few arguments given (1<4)

    It looks like the cause is that I included the ADC component with the following syntax:

    AD1 (demux\<3\:0\>) adc_4b one=vdd zero=0 num=demux_val

    one, zero, and num are defined with the veriloga "parameter" keyword, and the component has only one output (dout)

    I tried naming the terminals separately, as in:

    AD1 (demux\<3\> demux \<2\> demux\<1\> demux\<0\>) adc_4b one=vdd zero=0 num=demux_val

    And that worked

    But is there a way to use the bus notation? I have many other bus signals of varying lengths, so it would be cumbersome to expand the terminals.

    Thanks a lot

  • Andrew Beckett
    in reply to MT13

    No, as the Spectre language doesn’t really support the concept of busses. So you have to expand so that you have a collection of scalar nets. 

    One of the benefits of instantiating it in a Virtuoso schematic is that busses are then expanded by the netlisters. 

    Regards,

    Andrew

  • MT13
    in reply to Andrew Beckett

    Thank you very much

    All the best

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