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Reversing the contents of an expanded bus in VIVA

CADcasualty

In VIVA, when you expand a bus it yields (top to bottom) bus<LSB> ... bus<MSB>. I need the order reversed i.e. MSB on top. Is this possible?

And so we come to the part where you chime in and say "no, you lose".

Parents
  • CADcasualty

    Just providing some further clarification. I have declared a bus as follows:

    dout_bus = awvCreateBus("dout_bus" list( \
    L("/dout<17>") L("/dout<16>") \
    L("/dout<15>") L("/dout<14>") L("/dout<13>") L("/dout<12>") \
    L("/dout<11>") L("/dout<10>") L("/dout<9>") L("/dout<8>") \
    L("/dout<7>") L("/dout<6>") L("/dout<5>") L("/dout<4>") \
    L("/dout<3>") L("/dout<2>") L("/dout<1>") L("/dout<0>") ) "Binary")

    The L() function is something I wrote to convert a Verilog-A waveform into a digital waveform. When the bus is collapsed I see the contents in HEX and correctly derived from dout<17> ... dout<0>. So here's the part I think isn't so intuitive. When I expand the bus it shows me the waveforms:

    dout_bus[0]

    dout_bus[1]

    ...

    dout_bus[17]

    however the waveforms associated with each of the above are actually 

    dout<17>

    dout<16>

    ...

    dout<0>

    and that makes me confused. Am I doing something dumb?

Reply
  • CADcasualty

    Just providing some further clarification. I have declared a bus as follows:

    dout_bus = awvCreateBus("dout_bus" list( \
    L("/dout<17>") L("/dout<16>") \
    L("/dout<15>") L("/dout<14>") L("/dout<13>") L("/dout<12>") \
    L("/dout<11>") L("/dout<10>") L("/dout<9>") L("/dout<8>") \
    L("/dout<7>") L("/dout<6>") L("/dout<5>") L("/dout<4>") \
    L("/dout<3>") L("/dout<2>") L("/dout<1>") L("/dout<0>") ) "Binary")

    The L() function is something I wrote to convert a Verilog-A waveform into a digital waveform. When the bus is collapsed I see the contents in HEX and correctly derived from dout<17> ... dout<0>. So here's the part I think isn't so intuitive. When I expand the bus it shows me the waveforms:

    dout_bus[0]

    dout_bus[1]

    ...

    dout_bus[17]

    however the waveforms associated with each of the above are actually 

    dout<17>

    dout<16>

    ...

    dout<0>

    and that makes me confused. Am I doing something dumb?

Children
  • Andrew Beckett
    in reply to CADcasualty

    No, you're not doing something dumb. It doesn't really know what the original signals were once the bus was created - it just outputs them in a fixed order relative to the bits in the bus. I agree, it would be a good idea to have control over the order in which the bits were expanded, so you should contact customer support to request this (I didn't find any existing requests, but that doesn't mean it's not a reasonable request!)

    Regards,

    Andrew.

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