Cadence Liberate Characterization Help

Hi Anuradha,

First of all, please move to the latest Liberate release, 17.1.3.

When characterising leakage power, by default, the measured dc current will be multiplied by the supply voltage. This will result in a leakage value of 0 for all gnd supplies operating at 0 volts.

Leakage modelling depends on voltage_map, leakage_mode settings and leakage_add_input_pin in your script. You can find detailed explanation of different combinations and their impacts in the Liberate documentation. 

You may use extsim_deck_dir and extsim_save_passed/failed options to save the spice decks for each characterisation/arc/vector. After the run, you can run standalone Spectre simualtion and check the results.

Regards,

Guangjun

Hi, thanks for your reply Guang.

This is how my template for the inverter looks like : https://pastebin.com/1gYJHUP7

As per the reference manual, I use the default modes (haven't specified them explicitly) for voltage_map, leakage_mode and leakage_add_input_pin in above template. So that means, I am using following settings (1) for the leakage computation : 

But when I simulate this inverter schematic with parasitics in AE, the observed leakage power (IDDxVDD) when the input=1 (PMOS off) was 95.95 pW (87pA*1.1V). When the input=0 (NMOS off), this was found to be 190.01 pW (172.74 pA * 1.1V). But non of the leakage power values in the generated .lib file (https://pastebin.com/grfasa1s) for given input conditions do not match to these simulation values. Am I missing something here ? 

Anuradha

Since your VSS and V_input_low are both zero, VSS related power will be zero.

Hi, yes it is clear to me why the VSS pg power became 0. No issue of that 

The question I have is, as per my characterization library content (take a look at it : https://pastebin.com/grfasa1s),  even the leakage values I got for VDD pg_pin are wrong. i.e. 

leakage_power () {

      value : 0.0484719;

      when : "I&!ZN";

      related_pg_pin : VDD;

}

leakage_power () {

     value : 0.141881;

     when : "!I&ZN";

     related_pg_pin : VDD;

}

But when I simulate this inverter schematic with parasitics in AE, the observed leakage power (IDDxVDD) when the input=1 (PMOS off) was 95.95 pW (87pA*1.1V). When the input=0 (NMOS off), this was found to be 190.01 pW (172.74 pA * 1.1V). I used both internal and external (spectre) simulators for characterization (same PVT in both cases), but the result is same. Can anyone explain why the spice simulation values differ from the characterization result.

Thanks

Anuradha

Hi, yes it is clear to me why the VSS pg power became 0. No issue of that 

The question I have is, as per my characterization library content (take a look at it : https://pastebin.com/grfasa1s),  even the leakage values I got for VDD pg_pin are wrong. i.e. 

leakage_power () {

      value : 0.0484719;

      when : "I&!ZN";

      related_pg_pin : VDD;

}

leakage_power () {

     value : 0.141881;

     when : "!I&ZN";

     related_pg_pin : VDD;

}

But when I simulate this inverter schematic with parasitics in AE, the observed leakage power (IDDxVDD) when the input=1 (PMOS off) was 95.95 pW (87pA*1.1V). When the input=0 (NMOS off), this was found to be 190.01 pW (172.74 pA * 1.1V). I used both internal and external (spectre) simulators for characterization (same PVT in both cases), but the result is same. Can anyone explain why the spice simulation values differ from the characterization result.

Thanks

Anuradha

Sorry, but I though you were still asking about VSS related power in your last question.

To debug any characterized values, you can use the following commands to save the Spice deck. After the run, go to the specified deck_dir and open the map.lst file to find the corresponding subdirectory for each arc. Open the sim.sp and remove the save=none option. re-run this deck. After simulation, use VIAV to view the waveform. If there are differences between these results and your schematic simulations, look into the sim.sp. If you see anything wrong, we will need to have a full test case to investigate.

set_var extsim_deck_dir  <full_path_here>

set_var extsim_save_passed deck

Thanks, after running the spice deck, I was able to verify the issue......

Anuradha