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Cadence Liberate Characterization Help

anurans
anurans over 7 years ago

Hi All,

For the characterization of a standard cell library, I am using LIBERATE_15.14.070 version. The cell spice model was generated using IC6.1.5, and I am using Spectre as the external simulator for the characterization. I have a question specifically on the leakage_power nodes of the .lib file generated by Liberate. For an example, for a simple inverter, I ended up having leakage_power values as follows (in the link):

https://pastebin.com/grfasa1s

However the resulting leakage values do not follow the circuit simulation values in IC6-Spectre.

> Can anybody explain why the leakage value related to VSS pin is always 0 ? 

> How does the Liberate calculate these values ? Is there a way to evaluate the accuracy of Liberate-Spectre simulation ?

Thanks in advance

Anuradha

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  • sazjad
    sazjad over 7 years ago

    Hi Anuradha,

    I am also trying to generate .lib files using the Liberate tool. Since you have already gone through the process, can you please help me with one issue?
    I have created a netlist from my circuit and used it in liberate to generate .lib file. However, it seems like the generated netlist is not compatible with the liberate or maybe be I am missing something. Have you had a this kind of issue?

    Thanks in advance.

    Best regards.
    Hossain

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  • anurans
    anurans over 7 years ago in reply to sazjad

    Hi, can you be more specific about the issue you have ? Does Liberate give errors when reading the netlist ? 

    Anuradha

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  • sazjad
    sazjad over 7 years ago in reply to anurans

    Hi Anuradha,

    Thank you for your reply and I am sorry for my late response.

    I have tried with the sample run script, model file, and template provided with the Liberate tool and got the library creation working (shown in figure working_lib.png).
    However, when I tried with an extracted inverter netlist (attached inv_netlist_extracted.png) and 45nm NCSU PDK, the generated output is showing the cell_leakage_power as 0. In addition, the library that I have generated is not showing the inverter functionality like the other one (working_lib.png) is showing.

    I have attached the run script and template I am using. In addition, I have attached the working and incorrect generated library.


    Can you please take a look and see what might causes this issue?

    Thank you for your time.

    Best regards,

    Hossain




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  • Guangjun Cao
    Guangjun Cao over 7 years ago in reply to sazjad

    Hi Hossain,

    Did your characterisation run finish successfully? please check the logfile for any warning or errors. do you see INVX1 in the 'List of failing cells' at the end of your logfile? 

    For further debug, please use the following settings to save the spice decks and run standalone Spectre to check the simulation results.

    set_var extsim_deck_dir  <full_path_here>

    set_var extsim_save_passed deck

    set_var extsim_save_failed deck

    Regards,

    Guangjun

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  • sazjad
    sazjad over 7 years ago in reply to Guangjun Cao

    Hi Cao,

    I am not getting any error and characterization was finished successfully. None of the cells are listed in 'List of failing cells'.
    I have made the changes as you suggested but I am still seeing the "cell_leakage_power: 0" and "function: 0". 
    Can you please suggest anything else that might solve this issue?

    By the way, there are couple of folders generated in the spice deck. What is the proper way of debugging if there is any error?

    Thank you for your time and help.

    Best regards,
    Hossain.

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  • sazjad
    sazjad over 7 years ago in reply to Guangjun Cao

    Hi Cao,

    I am not getting any error and characterization was finished successfully. None of the cells are listed in 'List of failing cells'.
    I have made the changes as you suggested but I am still seeing the "cell_leakage_power: 0" and "function: 0". 
    Can you please suggest anything else that might solve this issue?

    By the way, there are couple of folders generated in the spice deck. What is the proper way of debugging if there is any error?

    Thank you for your time and help.

    Best regards,
    Hossain.

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  • Guangjun Cao
    Guangjun Cao over 7 years ago in reply to sazjad

    under the directory you specified with extsim_deck_dir, there are compressed files for each cell. unpack the corresponding tarball. you will see a map.lst file, which describes the mapping of arcs and directories. in each leaf directory, there is a sim.sp. open the file and remove save/nosave option. save a file and run spectre on this file. after the run, using Viva to view the waveform. For leakage, you need to refer to Liberate documentation on how leakage is calculated.

    With the char_library command option, you do not need any define_leakage or define_arc commands.

    there is also an example directory in liberate installation directory, which can be used as reference.

    Good luck.

    Guangjun 

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  • anurans
    anurans over 7 years ago in reply to sazjad

    Hi, Cao is right ! char_library automatically calculates leakage if not specifically written. 

    Anuradha

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  • sazjad
    sazjad over 7 years ago in reply to Guangjun Cao
    Hi Cao and Anuradha,

    Thank you for your suggestions. It seems like I can generate the .lib file successfully using the fictitious model file provided with the tool. However, whenever I am using NCSU 45nm model file, it's failing to show leakage power and function. I am assuming there are some compatibility issues between model files and netlist. Please correct me if I am wrong. 

    I have attached the inverter netlist here ( http://ge.tt/888n5zr2 ) that was extracted using NCSU 45nm PDK and also attached a copy of NCSU model file for NMOS here
    ( http://ge.tt/3J3w5zr2 )
    I have also attached the fictitious model file here ( http://ge.tt/6Wrt5zr2 ) that was provided with the tool.

    I have looked into the spice deck for both cases and I don't see any transistor or model file definition in the sim.sp (see http://ge.tt/6uw46zr2 ) for NCSU 45nm PDK as I have seen with fictitious model (see http://ge.tt/8gFz5zr2 ).

    Thank you so much for your time and help. Any suggestion would be very helpful.

    Thanks
    Hossain
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  • Guangjun Cao
    Guangjun Cao over 7 years ago in reply to sazjad

    I can not find out the reason with what you have provided. It could be some problems with your input data or the settings. Also, please try -extsim spectre option in your char_library command.  

    If you need further help, please submit a Case, and provide a test case with the run results as they are. 

    Regards,

    Guangjun

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  • sazjad
    sazjad over 7 years ago in reply to Guangjun Cao

    Hi Cao,

    I have used -extsim spectre option, but still having the same issue; its not generating the leakage power.
    Unfortunately I don't have the access to submit a case. I think as an academic user I only have access to online support database. I will keep trying to see if I can fix this issue.
    Thank you for your help and time.

    Best regards,

    Hossain

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  • Guangjun Cao
    Guangjun Cao over 7 years ago in reply to sazjad

    can you show me the full logfile?

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  • sazjad
    sazjad over 7 years ago in reply to Guangjun Cao

    Hi Cao,

    Sure. The log file is included in this (http://ge.tt/9DDpc4s2) link.

    Thank you.

    Best regards,
    Hossain

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  • Guangjun Cao
    Guangjun Cao over 7 years ago in reply to sazjad

    You are using a very old Liberate release. Please download the latest release first.

    There are many warnings in your logfile. The most critical one might be during netlist parsing, "Warning from parser during circuit read-in...". These warnings could mean no devices are recognized correctly.

    After "generating vectors...", you should see timing related information, in addition to power/leakage. But they do not exist. 

    So, the most possible issue is in your netlist and/or model files.

    regards,

    Guangjun

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  • Guangjun Cao
    Guangjun Cao over 7 years ago in reply to Guangjun Cao
    "/home/DREXEL/msh89/ECEC574/ecect680-s2017/LIBERATE_EXAMPLE/MODELS/include_SS.sp", line 7: Warning: Possible reason is that no section is specified when using statement .lib "
    From this message, it looks like you did not specify a corner section here.
    INFO (LIB-926): The definition of the sub-circuit or model for instance 'MM_i_1' could not be found. Run the following checks in the given sequence: the subcircuit or model is loaded, the first line in the model file is empty or has a comment, and the netlist syntax is correct. If no problem is found in these checks, use the 'define_leafcell' command to define the sub-circuit or model, and rerun Tcl.

    This message indicates you may have to use define_leafcell command to declare model for MM_i_1. This is typically required when you use exclusive_model_included and "char -extsim".
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  • anurans
    anurans over 6 years ago in reply to Guangjun Cao

    Hi Guangjun,

    Out of the curiosity I am asking, I know that "define_arc" command is not mandatory. But in Liberate example folder, the template used for re-characterization of the library (template_rechar_example.tcl) has defined several power/delay arcs for both sequential and combinatorial cells. Is it specifically done to shorten the .lib file content ? 

    Let's say for a simple dynamic double edge-triggerd flip-flop (shown below), is automatic arc determination by Liberate  (without define_arc) enough for accurate results ? 

    Thanks

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