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Transient PLL spur simulation setup

Ruixin

Hi, Officers, 

I have a question on how to accurate estimate the spur at PLL output by using transient simulation with DFT function in SpectreRF. 

For example, if the spur is located at 100 kHz offset from the PLL output with the power (or variation) of 1 ps, what would be proper 

setup for time step in transient simulation ? 

Do we need to set the time step to be smaller than 1 ps to extract this spur accurately in the simulation ? 

Sincerely, 

Ruixin 

Parents
  • Andrew Beckett

    I don't think you've given enough information here. First of all the "DFT" function isn't anything to do with SpectreRF (it's a calculator function) and then you're talking about transient simulation. What is generating these spurs? What kind of PLL is it? What is the frequency at the output of the PLL? You're talking about a spur with a power of 1ps (which is time - so I'm confused).

    I doubt very much that you need to set maxstep (that's nearly always the wrong solution for any problem, other than maybe getting oscillators to start). You might need to set strobe period for the DFT to be accurate, but I don't know what it would need to be given the rather sparse information you've provided so far...

    Regards,

    Andrew.

  • Ruixin
    in reply to Andrew Beckett

    Thanks, Andrew, 

    To be more specific, I have two cases, one is that I am simulating a multi-phase (16 Phases) VCO at 2.4 GHz with reference frequency 40 MHz in integer mode, and by sequentially selecting one of the phases to be back into PFD, the circuits can synthesize a fractional frequency with frequency offset 40MHz/16.  If the phase mismatch between each phase is around 1 ps, which actually introduces spurs at the output,  then in order to accurately predict the spur level at the synthesizer's output then what would be the proper max time step for it ? 

    Similarly, if we have a 16 multi-phase output with frequency at 200 MHz with square wave output with phase mismatch around 1 ps, then what would be proper setup for it ? 

    I am sorry that I actually set the max time step but not the time step, without time strobe. 

    Sincerely, 

    Ruixin

Reply
  • Ruixin
    in reply to Andrew Beckett

    Thanks, Andrew, 

    To be more specific, I have two cases, one is that I am simulating a multi-phase (16 Phases) VCO at 2.4 GHz with reference frequency 40 MHz in integer mode, and by sequentially selecting one of the phases to be back into PFD, the circuits can synthesize a fractional frequency with frequency offset 40MHz/16.  If the phase mismatch between each phase is around 1 ps, which actually introduces spurs at the output,  then in order to accurately predict the spur level at the synthesizer's output then what would be the proper max time step for it ? 

    Similarly, if we have a 16 multi-phase output with frequency at 200 MHz with square wave output with phase mismatch around 1 ps, then what would be proper setup for it ? 

    I am sorry that I actually set the max time step but not the time step, without time strobe. 

    Sincerely, 

    Ruixin

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