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  3. custom cap cell from tsmc 0.18um process

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custom cap cell from tsmc 0.18um process

DavidLou
DavidLou over 7 years ago

hello exports,

very dumb question, how should I customize a new cap cell so that I can build my circuits upon? I know I'll need cell symbol, layout, and DRC checked. how should the parasitics be extracted for various PVT corners? would it be possible to make it pcell? any comments or suggestions or points to tutorials will be greatly appreciated.

thanks,

David

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  • Andrew Beckett
    Andrew Beckett over 7 years ago

    Hi David,

    This is a better question for customer support as it's beyond what can reasonably be described in a forum response (would take too long, especially without knowing what you do and don't know already) - it's also not clear why you can't just use one of the foundry-provided capacitors. It would involve having to create the views you talked about, creating a simulation model, but you'd also need to create a pcell (say) and also ensure that the LVS deck recognised the device, and that the extraction tool knew not to double count parasitics and so on.

    Regards,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 7 years ago

    Hi David,

    This is a better question for customer support as it's beyond what can reasonably be described in a forum response (would take too long, especially without knowing what you do and don't know already) - it's also not clear why you can't just use one of the foundry-provided capacitors. It would involve having to create the views you talked about, creating a simulation model, but you'd also need to create a pcell (say) and also ensure that the LVS deck recognised the device, and that the extraction tool knew not to double count parasitics and so on.

    Regards,

    Andrew.

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  • DavidLou
    DavidLou over 7 years ago in reply to Andrew Beckett

    got it Andrew and thanks anyway. I thought it's quite usual practice. 

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