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Extract schematic from layout or verilog code

Navidrezara

Hello,

I am a full-custom analog designer but for my project I had to design a semi-custom part. I want to do an overall LVS but I cannot make netlist. I read a lot of article and web sites to do it but it is not clear at all. My technology is UMC180nm. The standard cell are provided by Faraday and they only provides layout (not only a symbol). So I cannot make any schematics from verilog. I also tried to make a netlist from layout to make a schematic afterwards but this also did not work. Can you please help me on this issue. My deadline is very close and I do not know how to do this.

Thank you so much in advance,

Best regards,

Reza

  • Andrew Beckett

    Hi Reza,

    You won't be able to produce a schematic of a standard cell from Verilog. You'll need a CDL or SPICE netlist - and I would expect that the standard cell provider would provide CDL netlists to allow you to LVS - it would be very strange if they didn't.

    So you should contact Faraday (or whoever provided the standard cell library) to get a CDL netlist - then you can use that for LVS.

    The alternative is to extract the devices from layout, but that's not an entirely trivial task (and involves too many questions about which tools you're using, what data is available) to reasonably answer in the forums (at least with the limited time I have this week). Far better to get the data from the provider rather than trying to reverse engineer it.

    Regards,

    Andrew.

  • Navidrezara
    in reply to Andrew Beckett

    Dear Andrew,

    Thank you so much for your fast reply. I will follow your guidance and I will ask europractice to provide CDL or SPICE files for me. I was thinking about making schematics for the logics that are used in the design. But if you say that it is complicated I wont go that way. Thank you a lot.

    Regards,

    Reza

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